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| author | Lee Leahy <leroy.p.leahy@intel.com> | 2016-07-20 08:58:58 -0700 |
|---|---|---|
| committer | Lee Leahy <leroy.p.leahy@intel.com> | 2016-08-03 17:47:53 +0200 |
| commit | 01728bb2ed1847dadf1429fafe0be2cb7876eed8 (patch) | |
| tree | dac9a0682b205409038d4b742350ba28e2dc1af3 /src/soc/intel/quark/include | |
| parent | 3d0e3cf4b125dfda236d6978adea5f5d40fd78e8 (diff) | |
| download | coreboot-01728bb2ed1847dadf1429fafe0be2cb7876eed8.tar.xz | |
soc/intel/quark: Prepare for FSP2.0 support
Split the original contents of romstage.c into car.c, romstage.c and
fsp1_1.c.
TEST=Build and run on Galileo Gen2
Change-Id: I6392d7382e383ea2087afa6bf45b1f087ba78d79
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15862
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/quark/include')
| -rw-r--r-- | src/soc/intel/quark/include/soc/pm.h | 1 | ||||
| -rw-r--r-- | src/soc/intel/quark/include/soc/ramstage.h | 1 | ||||
| -rw-r--r-- | src/soc/intel/quark/include/soc/romstage.h | 2 |
3 files changed, 4 insertions, 0 deletions
diff --git a/src/soc/intel/quark/include/soc/pm.h b/src/soc/intel/quark/include/soc/pm.h index 30d8841e34..7547a53605 100644 --- a/src/soc/intel/quark/include/soc/pm.h +++ b/src/soc/intel/quark/include/soc/pm.h @@ -24,6 +24,7 @@ struct chipset_power_state { uint32_t prev_sleep_state; } __attribute__ ((packed)); +struct chipset_power_state *get_power_state(void); struct chipset_power_state *fill_power_state(void); #endif diff --git a/src/soc/intel/quark/include/soc/ramstage.h b/src/soc/intel/quark/include/soc/ramstage.h index 80e2f0081b..9f201a0d20 100644 --- a/src/soc/intel/quark/include/soc/ramstage.h +++ b/src/soc/intel/quark/include/soc/ramstage.h @@ -23,5 +23,6 @@ #include <soc/QuarkNcSocId.h> void mainboard_gpio_i2c_init(device_t dev); +void fsp_silicon_init(void); #endif /* _SOC_RAMSTAGE_H_ */ diff --git a/src/soc/intel/quark/include/soc/romstage.h b/src/soc/intel/quark/include/soc/romstage.h index 7e761ab427..fcac3e20aa 100644 --- a/src/soc/intel/quark/include/soc/romstage.h +++ b/src/soc/intel/quark/include/soc/romstage.h @@ -26,6 +26,8 @@ #include <soc/reg_access.h> asmlinkage void *car_stage_c_entry(void); +void clear_smi_and_wake_events(void); +void disable_rom_shadow(void); void report_platform_info(void); int set_base_address_and_enable_uart(u8 bus, u8 dev, u8 func, u32 mmio_base); void pcie_init(void); |