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| author | Lee Leahy <leroy.p.leahy@intel.com> | 2016-05-15 13:32:24 -0700 |
|---|---|---|
| committer | Leroy P Leahy <leroy.p.leahy@intel.com> | 2016-05-17 20:26:28 +0200 |
| commit | 083da160af4a0e3a76506af59477f105d78b9683 (patch) | |
| tree | 7078353691e6607737d7e606a836106874b094a1 /src/soc/intel/quark/include | |
| parent | 4c56a58f63699dc54383dc4f8402d14ddbca5114 (diff) | |
| download | coreboot-083da160af4a0e3a76506af59477f105d78b9683.tar.xz | |
soc/intel/quark: Add GPIO register access
Add register access routines for the GPIO and legacy GPIO controllers.
TEST=Build and run on Galileo Gen2
Change-Id: I0c023428f4784de9e025279480554b8ed134afca
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/14825
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/soc/intel/quark/include')
| -rw-r--r-- | src/soc/intel/quark/include/soc/pci_devs.h | 8 | ||||
| -rw-r--r-- | src/soc/intel/quark/include/soc/reg_access.h | 48 |
2 files changed, 56 insertions, 0 deletions
diff --git a/src/soc/intel/quark/include/soc/pci_devs.h b/src/soc/intel/quark/include/soc/pci_devs.h index 176e77d2cb..4bf71acd3e 100644 --- a/src/soc/intel/quark/include/soc/pci_devs.h +++ b/src/soc/intel/quark/include/soc/pci_devs.h @@ -26,6 +26,7 @@ #define MC_BDF PCI_DEV(PCI_BUS_NUMBER_QNC, MC_DEV, MC_FUN) /* Device IDs */ +#define I2CGPIO_DEVID 0x0934 #define HSUART_DEVID 0x0936 #define EHCI_DEVID 0x0939 @@ -34,6 +35,13 @@ #define HSUART1_DEV SIO1_DEV #define HSUART1_FUNC 5 +/* IO Fabric 2 */ +#define SIO2_DEV 0x15 +#define I2CGPIO_DEV SIO2_DEV +#define I2CGPIO_FUNC 2 +#define I2CGPIO_DEV_FUNC PCI_DEVFN(I2CGPIO_DEV, I2CGPIO_FUNC) +#define I2CGPIO_BDF PCI_DEV(PCI_BUS_NUMBER_QNC, I2CGPIO_DEV, I2CGPIO_FUNC) + /* Platform Controller Unit */ #define LPC_DEV PCI_DEVICE_NUMBER_QNC_LPC #define LPC_FUNC PCI_FUNCTION_NUMBER_QNC_LPC diff --git a/src/soc/intel/quark/include/soc/reg_access.h b/src/soc/intel/quark/include/soc/reg_access.h index c6b786a36b..c1b0df007b 100644 --- a/src/soc/intel/quark/include/soc/reg_access.h +++ b/src/soc/intel/quark/include/soc/reg_access.h @@ -20,6 +20,7 @@ #include <fsp/util.h> #include <reg_script.h> #include <soc/IntelQNCConfig.h> +#include <soc/Ioh.h> #include <soc/QuarkNcSocId.h> enum { @@ -27,6 +28,8 @@ enum { SOC_UNIT_REGS, RMU_TEMP_REGS, MICROSECOND_DELAY, + LEG_GPIO_REGS, + GPIO_REGS, }; enum { @@ -38,6 +41,48 @@ enum { _REG_SCRIPT_ENCODE_RAW(REG_SCRIPT_COMMAND_##cmd_, SOC_TYPE, \ size_, reg_, mask_, value_, timeout_, reg_set_) +/* GPIO controller register access macros */ +#define REG_GPIO_ACCESS(cmd_, reg_, mask_, value_, timeout_) \ + SOC_ACCESS(cmd_, reg_, REG_SCRIPT_SIZE_32, mask_, value_, timeout_, \ + GPIO_REGS) +#define REG_GPIO_READ(reg_) \ + REG_GPIO_ACCESS(READ, reg_, 0, 0, 0) +#define REG_GPIO_WRITE(reg_, value_) \ + REG_GPIO_ACCESS(WRITE, reg_, 0, value_, 0) +#define REG_GPIO_AND(reg_, value_) \ + REG_GPIO_RMW(reg_, value_, 0) +#define REG_GPIO_RMW(reg_, mask_, value_) \ + REG_GPIO_ACCESS(RMW, reg_, mask_, value_, 0) +#define REG_GPIO_RXW(reg_, mask_, value_) \ + REG_GPIO_ACCESS(RXW, reg_, mask_, value_, 0) +#define REG_GPIO_OR(reg_, value_) \ + REG_GPIO_RMW(reg_, 0xffffffff, value_) +#define REG_GPIO_POLL(reg_, mask_, value_, timeout_) \ + REG_GPIO_ACCESS(POLL, reg_, mask_, value_, timeout_) +#define REG_GPIO_XOR(reg_, value_) \ + REG_GPIO_RXW(reg_, 0xffffffff, value_) + +/* Legacy GPIO register access macros */ +#define REG_LEG_GPIO_ACCESS(cmd_, reg_, mask_, value_, timeout_) \ + SOC_ACCESS(cmd_, reg_, REG_SCRIPT_SIZE_32, mask_, value_, timeout_, \ + LEG_GPIO_REGS) +#define REG_LEG_GPIO_READ(reg_) \ + REG_LEG_GPIO_ACCESS(READ, reg_, 0, 0, 0) +#define REG_LEG_GPIO_WRITE(reg_, value_) \ + REG_LEG_GPIO_ACCESS(WRITE, reg_, 0, value_, 0) +#define REG_LEG_GPIO_AND(reg_, value_) \ + REG_LEG_GPIO_RMW(reg_, value_, 0) +#define REG_LEG_GPIO_RMW(reg_, mask_, value_) \ + REG_LEG_GPIO_ACCESS(RMW, reg_, mask_, value_, 0) +#define REG_LEG_GPIO_RXW(reg_, mask_, value_) \ + REG_LEG_GPIO_ACCESS(RXW, reg_, mask_, value_, 0) +#define REG_LEG_GPIO_OR(reg_, value_) \ + REG_LEG_GPIO_RMW(reg_, 0xffffffff, value_) +#define REG_LEG_GPIO_POLL(reg_, mask_, value_, timeout_) \ + REG_LEG_GPIO_ACCESS(POLL, reg_, mask_, value_, timeout_) +#define REG_LEG_GPIO_XOR(reg_, value_) \ + REG_LEG_GPIO_RXW(reg_, 0xffffffff, value_) + /* RMU temperature register access macros */ #define REG_RMU_TEMP_ACCESS(cmd_, reg_, mask_, value_, timeout_) \ SOC_ACCESS(cmd_, reg_, REG_SCRIPT_SIZE_32, mask_, value_, timeout_, \ @@ -105,10 +150,13 @@ enum { #define REG_USB_XOR(reg_, value_) \ REG_USB_RXW(reg_, 0xffffffff, value_) +void mainboard_gpio_init(void); void mcr_write(uint8_t opcode, uint8_t port, uint32_t reg_address); uint32_t mdr_read(void); void mdr_write(uint32_t value); void mea_write(uint32_t reg_address); +uint32_t reg_legacy_gpio_read(uint32_t reg_address); +void reg_legacy_gpio_write(uint32_t reg_address, uint32_t value); uint32_t reg_rmu_temp_read(uint32_t reg_address); #endif /* _QUARK_REG_ACCESS_H_ */ |