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authorLee Leahy <leroy.p.leahy@intel.com>2016-07-25 07:41:54 -0700
committerLee Leahy <leroy.p.leahy@intel.com>2016-08-05 01:50:45 +0200
commit102f6253600cfa3f741c0d1d126436d612daa203 (patch)
treedc3d0c6376b405dc053e4f4c9c864d30cf4737eb /src/soc/intel/quark/include
parent6e05c33626e128c383470579f423b1ee569302ba (diff)
downloadcoreboot-102f6253600cfa3f741c0d1d126436d612daa203.tar.xz
soc/intel/quark: Add FSP 2.0 boot block support
Add the pieces necessary to successfully build and run bootblock using the FSP 2.0 build. TEST=Build and run bootblock on Galileo Gen2 Change-Id: I2377f0b0147196f100396b8cd7eaca8f92d6932f Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/15865 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/soc/intel/quark/include')
-rw-r--r--src/soc/intel/quark/include/soc/car.h29
-rw-r--r--src/soc/intel/quark/include/soc/ramstage.h4
-rw-r--r--src/soc/intel/quark/include/soc/romstage.h4
3 files changed, 37 insertions, 0 deletions
diff --git a/src/soc/intel/quark/include/soc/car.h b/src/soc/intel/quark/include/soc/car.h
new file mode 100644
index 0000000000..23c6a24fbf
--- /dev/null
+++ b/src/soc/intel/quark/include/soc/car.h
@@ -0,0 +1,29 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2016 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _SOC_CAR_H_
+#define _SOC_CAR_H_
+
+#include <fsp/util.h>
+
+/* Mainboard and SoC initialization prior to console. */
+void car_mainboard_pre_console_init(void);
+void car_soc_pre_console_init(void);
+
+/* Mainboard and SoC initialization post console initialization. */
+void car_mainboard_post_console_init(void);
+void car_soc_post_console_init(void);
+
+#endif /* _SOC_CAR_H_ */
diff --git a/src/soc/intel/quark/include/soc/ramstage.h b/src/soc/intel/quark/include/soc/ramstage.h
index 9f201a0d20..d97db747c3 100644
--- a/src/soc/intel/quark/include/soc/ramstage.h
+++ b/src/soc/intel/quark/include/soc/ramstage.h
@@ -19,10 +19,14 @@
#include <chip.h>
#include <device/device.h>
+#if IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1)
#include <fsp/ramstage.h>
+#endif
#include <soc/QuarkNcSocId.h>
void mainboard_gpio_i2c_init(device_t dev);
+#if IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1)
void fsp_silicon_init(void);
+#endif
#endif /* _SOC_RAMSTAGE_H_ */
diff --git a/src/soc/intel/quark/include/soc/romstage.h b/src/soc/intel/quark/include/soc/romstage.h
index fcac3e20aa..d6f9186754 100644
--- a/src/soc/intel/quark/include/soc/romstage.h
+++ b/src/soc/intel/quark/include/soc/romstage.h
@@ -22,7 +22,11 @@
#error "Don't include romstage.h from a ramstage compilation unit!"
#endif
+#if IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1)
#include <fsp/romstage.h>
+#else
+#include <soc/car.h>
+#endif
#include <soc/reg_access.h>
asmlinkage void *car_stage_c_entry(void);