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authorLee Leahy <leroy.p.leahy@intel.com>2016-05-30 15:01:06 -0700
committerLeroy P Leahy <leroy.p.leahy@intel.com>2016-05-31 22:11:51 +0200
commitbc518d5cab4234a0d0d06a7d3829bbca9e318ba6 (patch)
tree09eb5cf6c3476c17ca34fde7164d14c2f2ec3b0b /src/soc/intel/quark/include
parentac78db3a53a7653a73409936455d68c754291e9d (diff)
downloadcoreboot-bc518d5cab4234a0d0d06a7d3829bbca9e318ba6.tar.xz
quark: Enable HSUART0 as console
The use of HSUART0 on galileo requires early initialization of the I2C GPIO expanders to direct the RXD and TXD signals to DIGITAL 0 and 1 on the expansion connector. TEST=None Change-Id: I11195d79e954c1f6bc91eafe257d7ddc1310b2e7 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/15010 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/soc/intel/quark/include')
-rw-r--r--src/soc/intel/quark/include/soc/pci_devs.h3
-rw-r--r--src/soc/intel/quark/include/soc/reg_access.h1
2 files changed, 3 insertions, 1 deletions
diff --git a/src/soc/intel/quark/include/soc/pci_devs.h b/src/soc/intel/quark/include/soc/pci_devs.h
index 278a012d11..0c99eb9de4 100644
--- a/src/soc/intel/quark/include/soc/pci_devs.h
+++ b/src/soc/intel/quark/include/soc/pci_devs.h
@@ -33,11 +33,14 @@
/* IO Fabric 1 */
#define SIO1_DEV 0x14
+#define HSUART0_DEV SIO1_DEV
#define HSUART1_DEV SIO1_DEV
+#define HSUART0_FUNC 1
#define USB_DEV_PORT_FUNC 2
#define EHCI_FUNC 3
#define OHCI_FUNC 4
#define HSUART1_FUNC 5
+#define HSUART0_BDF PCI_DEV(PCI_BUS_NUMBER_QNC, HSUART0_DEV, HSUART0_FUNC)
#define HSUART1_BDF PCI_DEV(PCI_BUS_NUMBER_QNC, HSUART1_DEV, HSUART1_FUNC)
/* IO Fabric 2 */
diff --git a/src/soc/intel/quark/include/soc/reg_access.h b/src/soc/intel/quark/include/soc/reg_access.h
index e7a8963b8c..b934032358 100644
--- a/src/soc/intel/quark/include/soc/reg_access.h
+++ b/src/soc/intel/quark/include/soc/reg_access.h
@@ -203,7 +203,6 @@ enum {
REG_USB_RXW(reg_, 0xffffffff, value_)
void *get_i2c_address(void);
-void mainboard_gpio_init(void);
void mainboard_gpio_pcie_reset(uint32_t pin_value);
void mcr_write(uint8_t opcode, uint8_t port, uint32_t reg_address);
uint32_t mdr_read(void);