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authorLee Leahy <leroy.p.leahy@intel.com>2016-03-04 16:49:40 -0800
committerMartin Roth <martinroth@google.com>2016-03-21 19:46:59 +0100
commitd75ed0bfd9238b210fdca136784cd699696421c7 (patch)
tree403700be6619d403c68bbd866f5cdc47195fdfbf /src/soc/intel/quark/include
parent1f1f2c4d38dc5b58e0051f9d80086bc2a083a7cd (diff)
downloadcoreboot-d75ed0bfd9238b210fdca136784cd699696421c7.tar.xz
soc/intel/quark: Disable the ROM shadow
Disable the ROM shadow and enable RAM for 0x000e0000 - 0x000fffff. Testing on Galileo: * Edit the src/mainboard/intel/galileo/Makefile.inc file: * Add "select ADD_FSP_PDAT_FILE" * Add "select ADD_FSP_RAW_BIN" * Add "select ADD_RMU_FILE" * Place the FSP.bin file in the location specified by CONFIG_FSP_FILE * Place the pdat.bin files in the location specified by CONFIG_FSP_PDAT_FILE * Place the rmu.bin file in the location specified by CONFIG_RMU_FILE * Build EDK2 CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc to generate UEFIPAYLOAD.fd * Testing successful display of 0x000ffff0 - 0x000fffff does not match the end of the SPI flash. Change-Id: I6e0a50417815320333eae0b69b96280c39db7eaa Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/14110 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/soc/intel/quark/include')
-rw-r--r--src/soc/intel/quark/include/soc/QuarkNcSocId.h2
-rw-r--r--src/soc/intel/quark/include/soc/romstage.h2
2 files changed, 4 insertions, 0 deletions
diff --git a/src/soc/intel/quark/include/soc/QuarkNcSocId.h b/src/soc/intel/quark/include/soc/QuarkNcSocId.h
index 1bf7e06b0b..22324465cb 100644
--- a/src/soc/intel/quark/include/soc/QuarkNcSocId.h
+++ b/src/soc/intel/quark/include/soc/QuarkNcSocId.h
@@ -269,6 +269,8 @@ Definitions beginning with "N_" are the bit position
//
#define QNC_MSG_FSBIC_REG_HMISC 0x03 // Host Misellaneous Controls
#define SMI_EN (BIT19) // SMI Global Enable (from Legacy Bridge)
+#define FSEG_RD_DRAM (BIT2) // Enable RAM for 0x000f0000 - 0x000fffff
+#define ESEG_RD_DRAM (BIT1) // Enable RAM for 0x000e0000 - 0x000effff
#define QNC_MSG_FSBIC_REG_HSMMC 0x04 // Host SMM Control
#define NON_HOST_SMM_WR_OPEN (BIT18) // SMM Writes OPEN
#define NON_HOST_SMM_RD_OPEN (BIT17) // SMM Writes OPEN
diff --git a/src/soc/intel/quark/include/soc/romstage.h b/src/soc/intel/quark/include/soc/romstage.h
index 23c62704a9..c2c7e9c03a 100644
--- a/src/soc/intel/quark/include/soc/romstage.h
+++ b/src/soc/intel/quark/include/soc/romstage.h
@@ -30,6 +30,8 @@ void mcr_write(uint8_t opcode, uint8_t port, uint32_t reg_address);
uint32_t mdr_read(void);
void mdr_write(uint32_t value);
void mea_write(uint32_t reg_address);
+uint32_t port_reg_read(uint8_t port, uint32_t offset);
+void port_reg_write(uint8_t port, uint32_t offset, uint32_t value);
void report_platform_info(void);
int set_base_address_and_enable_uart(u8 bus, u8 dev, u8 func, u32 mmio_base);