diff options
| author | Lee Leahy <leroy.p.leahy@intel.com> | 2016-05-15 15:12:56 -0700 |
|---|---|---|
| committer | Leroy P Leahy <leroy.p.leahy@intel.com> | 2016-05-18 00:57:48 +0200 |
| commit | ac690b1e9ba1318375bc7fba088aef5c7e3c07ce (patch) | |
| tree | 1edc12e74d4f994047b43f687d846a5076e915ce /src/soc/intel/quark/reg_access.c | |
| parent | 0e962eeb93741a9116e201aa52ab7bb966dfd482 (diff) | |
| download | coreboot-ac690b1e9ba1318375bc7fba088aef5c7e3c07ce.tar.xz | |
soc/intel/quark: Add I2C support
Add the I2C driver.
TEST=Build and run on Galileo Gen2
Change-Id: I53fdac93667a8ffb2c2c8f394334de2dece63d66
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/14828
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/soc/intel/quark/reg_access.c')
| -rw-r--r-- | src/soc/intel/quark/reg_access.c | 65 |
1 files changed, 39 insertions, 26 deletions
diff --git a/src/soc/intel/quark/reg_access.c b/src/soc/intel/quark/reg_access.c index 48d55210d3..4734135b2c 100644 --- a/src/soc/intel/quark/reg_access.c +++ b/src/soc/intel/quark/reg_access.c @@ -20,6 +20,45 @@ #include <soc/pci_devs.h> #include <soc/reg_access.h> +static uint32_t *get_gpio_address(uint32_t reg_address) +{ + uint32_t gpio_base_address; + + /* Get the GPIO base address */ + gpio_base_address = pci_read_config32(I2CGPIO_BDF, PCI_BASE_ADDRESS_1); + gpio_base_address &= ~PCI_BASE_ADDRESS_MEM_ATTR_MASK; + ASSERT (gpio_base_address != 0x00000000); + + /* Return the GPIO register address */ + return (uint32_t *)(gpio_base_address + reg_address); +} + +void *get_i2c_address(void) +{ + uint32_t gpio_base_address; + + /* Get the GPIO base address */ + gpio_base_address = pci_read_config32(I2CGPIO_BDF, PCI_BASE_ADDRESS_0); + gpio_base_address &= ~PCI_BASE_ADDRESS_MEM_ATTR_MASK; + ASSERT (gpio_base_address != 0x00000000); + + /* Return the GPIO register address */ + return (void *)gpio_base_address; +} + +static uint16_t get_legacy_gpio_address(uint32_t reg_address) +{ + uint32_t gpio_base_address; + + /* Get the GPIO base address */ + gpio_base_address = pci_read_config32(LPC_BDF, R_QNC_LPC_GBA_BASE); + ASSERT (gpio_base_address >= 0x80000000); + gpio_base_address &= B_QNC_LPC_GPA_BASE_MASK; + + /* Return the GPIO register address */ + return (uint16_t)(gpio_base_address + reg_address); +} + void mcr_write(uint8_t opcode, uint8_t port, uint32_t reg_address) { pci_write_config32(MC_BDF, QNC_ACCESS_PORT_MCR, @@ -45,19 +84,6 @@ void mea_write(uint32_t reg_address) & QNC_MEA_MASK); } -static uint32_t *get_gpio_address(uint32_t reg_address) -{ - uint32_t gpio_base_address; - - /* Get the GPIO base address */ - gpio_base_address = pci_read_config32(I2CGPIO_BDF, PCI_BASE_ADDRESS_1); - gpio_base_address &= ~PCI_BASE_ADDRESS_MEM_ATTR_MASK; - ASSERT (gpio_base_address != 0x00000000); - - /* Return the GPIO register address */ - return (uint32_t *)(gpio_base_address + reg_address); -} - static uint32_t reg_gpio_read(uint32_t reg_address) { /* Read the GPIO register */ @@ -70,19 +96,6 @@ static void reg_gpio_write(uint32_t reg_address, uint32_t value) *get_gpio_address(reg_address) = value; } -static uint16_t get_legacy_gpio_address(uint32_t reg_address) -{ - uint32_t gpio_base_address; - - /* Get the GPIO base address */ - gpio_base_address = pci_read_config32(LPC_BDF, R_QNC_LPC_GBA_BASE); - ASSERT (gpio_base_address >= 0x80000000); - gpio_base_address &= B_QNC_LPC_GPA_BASE_MASK; - - /* Return the GPIO register address */ - return (uint16_t)(gpio_base_address + reg_address); -} - uint32_t reg_legacy_gpio_read(uint32_t reg_address) { /* Read the legacy GPIO register */ |