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| author | Lee Leahy <leroy.p.leahy@intel.com> | 2017-04-01 20:33:58 -0700 |
|---|---|---|
| committer | Lee Leahy <leroy.p.leahy@intel.com> | 2017-05-08 19:13:35 +0200 |
| commit | 16bc9bab2ab3b248f44bdf721ec83cdc21bcc32e (patch) | |
| tree | 4d52e7ae44b49d4f63b21c74a255c47389e6bfeb /src/soc/intel/quark/romstage/fsp2_0.c | |
| parent | 52f29743b153e89ca38db5d7a207c676c4c70207 (diff) | |
| download | coreboot-16bc9bab2ab3b248f44bdf721ec83cdc21bcc32e.tar.xz | |
soc/intel/quark: Add SD/MMC test support
The SD/MMC test support consists of:
* Add Kconfig value to enable the SD/MMC test support.
* Add Kconfig value to enable the logging support.
* Add SD/MMC controller init code and read block 0 from each partition.
* Add logging code to snapshot the transactions with the SD/MMC device.
* Add eMMC driver for ramstage to call test code.
* Add romstage code to call test code.
* Add bootblock code to call test code.
TEST=Build and run on Galileo Gen2
Change-Id: I72785f0dcd466c05c1385cef166731219b583551
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/19211
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/soc/intel/quark/romstage/fsp2_0.c')
| -rw-r--r-- | src/soc/intel/quark/romstage/fsp2_0.c | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/src/soc/intel/quark/romstage/fsp2_0.c b/src/soc/intel/quark/romstage/fsp2_0.c index d03545d759..10e44c1b68 100644 --- a/src/soc/intel/quark/romstage/fsp2_0.c +++ b/src/soc/intel/quark/romstage/fsp2_0.c @@ -19,10 +19,12 @@ #include "../chip.h" #include <cpu/x86/cache.h> #include <fsp/util.h> +#include <soc/iomap.h> #include <soc/pci_devs.h> #include <soc/pm.h> #include <soc/romstage.h> #include <soc/reg_access.h> +#include <soc/storage_test.h> asmlinkage void *car_stage_c_entry(void) { @@ -34,6 +36,21 @@ asmlinkage void *car_stage_c_entry(void) post_code(0x20); console_init(); + if (IS_ENABLED(CONFIG_STORAGE_TEST)) { + uint32_t bar; + dev_t dev; + uint32_t previous_bar; + uint16_t previous_command; + + /* Enable the SD/MMC controller and run the test. Restore + * the BAR and command registers upon completion. + */ + dev = PCI_DEV(0, SD_MMC_DEV, SD_MMC_FUNC); + bar = storage_test_init(dev, &previous_bar, &previous_command); + storage_test(bar, 1); + storage_test_complete(dev, previous_bar, previous_command); + } + /* Initialize DRAM */ s3wake = fill_power_state() == ACPI_S3; fsp_memory_init(s3wake); |