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authorLee Leahy <leroy.p.leahy@intel.com>2017-03-13 16:37:20 -0700
committerLee Leahy <leroy.p.leahy@intel.com>2017-03-15 05:12:15 +0100
commit70bb05715ad0fa8edecb2185e1c1373c76ee2128 (patch)
treee4906fba38ed957aa678a8b1a6a18241305c8f04 /src/soc/intel/quark/romstage/fsp2_0.c
parent36984d85e758bd7b280a835c5c6e5c68b10e82b6 (diff)
downloadcoreboot-70bb05715ad0fa8edecb2185e1c1373c76ee2128.tar.xz
soc/intel/quark: Read the rmu.bin file from read-only region
Always read the rmu.bin file from the read-only section of the SPI flash. Without this change vboot attempts to read this file from the A or B section of the flash. TEST=Build and run on Galileo Gen2 Change-Id: Ied8eaa2cd37645bf401aa957936943946bfd6182 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/18803 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/quark/romstage/fsp2_0.c')
-rw-r--r--src/soc/intel/quark/romstage/fsp2_0.c14
1 files changed, 6 insertions, 8 deletions
diff --git a/src/soc/intel/quark/romstage/fsp2_0.c b/src/soc/intel/quark/romstage/fsp2_0.c
index 4d7f7c9479..d03545d759 100644
--- a/src/soc/intel/quark/romstage/fsp2_0.c
+++ b/src/soc/intel/quark/romstage/fsp2_0.c
@@ -15,7 +15,6 @@
#include <arch/early_variables.h>
#include <console/console.h>
-#include <cbfs.h>
#include <cbmem.h>
#include "../chip.h"
#include <cpu/x86/cache.h>
@@ -92,17 +91,16 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *fspm_upd, uint32_t version)
FSPM_ARCH_UPD *aupd;
const struct device *dev;
const struct soc_intel_quark_config *config;
- char *rmu_file;
- size_t rmu_file_len;
+ void *rmu_data;
+ size_t rmu_data_len;
FSP_M_CONFIG *upd;
/* Clear SMI and wake events */
clear_smi_and_wake_events();
/* Locate the RMU data file in flash */
- rmu_file = cbfs_boot_map_with_leak("rmu.bin", CBFS_TYPE_RAW,
- &rmu_file_len);
- if (!rmu_file)
+ rmu_data = locate_rmu_file(&rmu_data_len);
+ if (!rmu_data)
die("Microcode file (rmu.bin) not found.");
/* Locate the configuration data from devicetree.cb */
@@ -157,8 +155,8 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *fspm_upd, uint32_t version)
upd->Flags = config->Flags;
upd->FspReservedMemoryLength = config->FspReservedMemoryLength;
upd->RankMask = config->RankMask;
- upd->RmuBaseAddress = (uintptr_t)rmu_file;
- upd->RmuLength = rmu_file_len;
+ upd->RmuBaseAddress = (uintptr_t)rmu_data;
+ upd->RmuLength = rmu_data_len;
upd->SerialPortWriteChar = console_log_level(BIOS_SPEW)
? (uintptr_t)fsp_write_line : 0;
upd->SmmTsegSize = IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) ?