diff options
author | Julius Werner <jwerner@chromium.org> | 2019-03-05 16:53:33 -0800 |
---|---|---|
committer | Patrick Georgi <pgeorgi@google.com> | 2019-03-08 08:33:24 +0000 |
commit | cd49cce7b70e80b4acc49b56bb2bb94370b4d867 (patch) | |
tree | 8e89136e2da7cf54453ba8c112eda94415b56242 /src/soc/intel/quark/romstage/fsp2_0.c | |
parent | b3a8cc54dbaf833c590a56f912209a5632b71f49 (diff) | |
download | coreboot-cd49cce7b70e80b4acc49b56bb2bb94370b4d867.tar.xz |
coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)
This patch is a raw application of
find src/ -type f | xargs sed -i -e 's/IS_ENABLED\s*(CONFIG_/CONFIG(/g'
Change-Id: I6262d6d5c23cabe23c242b4f38d446b74fe16b88
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31774
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/soc/intel/quark/romstage/fsp2_0.c')
-rw-r--r-- | src/soc/intel/quark/romstage/fsp2_0.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/soc/intel/quark/romstage/fsp2_0.c b/src/soc/intel/quark/romstage/fsp2_0.c index c237da5270..31e130a398 100644 --- a/src/soc/intel/quark/romstage/fsp2_0.c +++ b/src/soc/intel/quark/romstage/fsp2_0.c @@ -36,7 +36,7 @@ asmlinkage void *car_stage_c_entry(void) post_code(0x20); console_init(); - if (IS_ENABLED(CONFIG_STORAGE_TEST)) { + if (CONFIG(STORAGE_TEST)) { uint32_t bar; pci_devfn_t dev; uint32_t previous_bar; @@ -132,7 +132,7 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *fspm_upd, uint32_t version) aupd->BootMode = FSP_BOOT_WITH_FULL_CONFIGURATION; /* Display the ESRAM layout */ - if (IS_ENABLED(CONFIG_DISPLAY_ESRAM_LAYOUT)) { + if (CONFIG(DISPLAY_ESRAM_LAYOUT)) { printk(BIOS_SPEW, "\nESRAM Layout:\n\n"); printk(BIOS_SPEW, "+-------------------+ 0x80080000 - ESRAM end\n"); @@ -175,7 +175,7 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *fspm_upd, uint32_t version) upd->RmuLength = rmu_data_len; upd->SerialPortWriteChar = !!console_log_level(BIOS_SPEW) ? (uintptr_t)fsp_write_line : 0; - upd->SmmTsegSize = IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) ? + upd->SmmTsegSize = CONFIG(HAVE_SMI_HANDLER) ? config->SmmTsegSize : 0; upd->SocRdOdtVal = config->SocRdOdtVal; upd->SocWrRonVal = config->SocWrRonVal; |