diff options
author | Lee Leahy <leroy.p.leahy@intel.com> | 2016-03-04 16:49:40 -0800 |
---|---|---|
committer | Martin Roth <martinroth@google.com> | 2016-03-21 19:46:59 +0100 |
commit | d75ed0bfd9238b210fdca136784cd699696421c7 (patch) | |
tree | 403700be6619d403c68bbd866f5cdc47195fdfbf /src/soc/intel/quark/romstage/mtrr.c | |
parent | 1f1f2c4d38dc5b58e0051f9d80086bc2a083a7cd (diff) | |
download | coreboot-d75ed0bfd9238b210fdca136784cd699696421c7.tar.xz |
soc/intel/quark: Disable the ROM shadow
Disable the ROM shadow and enable RAM for 0x000e0000 - 0x000fffff.
Testing on Galileo:
* Edit the src/mainboard/intel/galileo/Makefile.inc file:
* Add "select ADD_FSP_PDAT_FILE"
* Add "select ADD_FSP_RAW_BIN"
* Add "select ADD_RMU_FILE"
* Place the FSP.bin file in the location specified by CONFIG_FSP_FILE
* Place the pdat.bin files in the location specified by
CONFIG_FSP_PDAT_FILE
* Place the rmu.bin file in the location specified by CONFIG_RMU_FILE
* Build EDK2 CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc to generate
UEFIPAYLOAD.fd
* Testing successful display of 0x000ffff0 - 0x000fffff does not match
the end of the SPI flash.
Change-Id: I6e0a50417815320333eae0b69b96280c39db7eaa
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/14110
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/soc/intel/quark/romstage/mtrr.c')
-rw-r--r-- | src/soc/intel/quark/romstage/mtrr.c | 37 |
1 files changed, 23 insertions, 14 deletions
diff --git a/src/soc/intel/quark/romstage/mtrr.c b/src/soc/intel/quark/romstage/mtrr.c index a0313fb0a0..1528e17e09 100644 --- a/src/soc/intel/quark/romstage/mtrr.c +++ b/src/soc/intel/quark/romstage/mtrr.c @@ -73,6 +73,23 @@ static uint32_t mtrr_index_to_host_bridge_register_offset(unsigned long index) return offset; } +uint32_t port_reg_read(uint8_t port, uint32_t offset) +{ + /* Read the port register */ + offset = QNC_MSG_FSBIC_REG_HMISC; + mea_write(offset); + mcr_write(QUARK_OPCODE_READ, port, offset); + return mdr_read(); +} + +void port_reg_write(uint8_t port, uint32_t offset, uint32_t value) +{ + /* Write the port register */ + mea_write(offset); + mdr_write(value); + mcr_write(QUARK_OPCODE_WRITE, port, offset); +} + msr_t soc_mtrr_read(unsigned long index) { uint32_t offset; @@ -83,18 +100,14 @@ msr_t soc_mtrr_read(unsigned long index) /* Read the low 32-bits of the register */ offset = mtrr_index_to_host_bridge_register_offset(index); - mea_write(offset); - mcr_write(QUARK_OPCODE_READ, QUARK_NC_HOST_BRIDGE_SB_PORT_ID, offset); - value.u64 = mdr_read(); + value.u64 = port_reg_read(QUARK_NC_HOST_BRIDGE_SB_PORT_ID, offset); /* For 64-bit registers, read the upper 32-bits */ if ((offset >= QUARK_NC_HOST_BRIDGE_MTRR_FIX64K_00000) && (offset <= QUARK_NC_HOST_BRIDGE_MTRR_FIX4K_F8000)) { offset += 1; - mea_write(offset); - mcr_write(QUARK_OPCODE_READ, QUARK_NC_HOST_BRIDGE_SB_PORT_ID, - offset); - value.u64 |= mdr_read(); + value.u64 |= port_reg_read(QUARK_NC_HOST_BRIDGE_SB_PORT_ID, + offset); } return value.msr; } @@ -110,18 +123,14 @@ void soc_mtrr_write(unsigned long index, msr_t msr) /* Write the low 32-bits of the register */ value.msr = msr; offset = mtrr_index_to_host_bridge_register_offset(index); - mea_write(offset); - mdr_write(value.u32[0]); - mcr_write(QUARK_OPCODE_WRITE, QUARK_NC_HOST_BRIDGE_SB_PORT_ID, offset); + port_reg_write(QUARK_NC_HOST_BRIDGE_SB_PORT_ID, offset, value.u32[0]); /* For 64-bit registers, write the upper 32-bits */ if ((offset >= QUARK_NC_HOST_BRIDGE_MTRR_FIX64K_00000) && (offset <= QUARK_NC_HOST_BRIDGE_MTRR_FIX4K_F8000)) { offset += 1; - mea_write(offset); - mdr_write(value.u32[1]); - mcr_write(QUARK_OPCODE_WRITE, QUARK_NC_HOST_BRIDGE_SB_PORT_ID, - offset); + port_reg_write(QUARK_NC_HOST_BRIDGE_SB_PORT_ID, offset, + value.u32[1]); } } |