soc/intel/quark: Set the UPD values for MemoryInit

Set the UPD values for MemoryInit.
*  Update the FspUpdVpd.h file which specifies the parameters for
   MemoryInit.
*  Add the necessary values to chip.h to enable values to come from
   the mainboard's devicetree.cb file
*  Add the parameters to the mainboard's devicetree.cb file
*  Locate the platform configuration database file (pdat.bin)
*  Copy the data values from the chip_info structure into the UPDs
*  Display the UPD values

Testing on Galileo:
*  Edit the src/mainboard/intel/galileo/Makefile.inc file:
   *  Add "select ADD_FSP_PDAT_FILE"
   *  Add "select ADD_FSP_RAW_BIN"
   *  Add "select ADD_RMU_FILE"
*  Place the FSP.bin file in the location specified by CONFIG_FSP_FILE
*  Place the pdat.bin files in the location specified by
   CONFIG_FSP_PDAT_FILE
*  Place the rmu.bin file in the location specified by CONFIG_RMU_FILE
*  Build EDK2 CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc to generate
   UEFIPAYLOAD.fd
*  Edit .config file and add the following lines:
   *  CONFIG_DISPLAY_UPD_DATA=y
*  Testing successful when the UPD data is displayed before the call to
   MemoryInit

Change-Id: Ic64f3d97eb43ea42d9b149769fc96bf78bf804f5
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/13896
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)

1 files changed, 54 insertions, 0 deletions

diff --git a/src/soc/intel/quark/romstage/romstage.c b/src/soc/intel/quark/romstage/romstage.c
index 731e52975d..a089185bd0 100644
--- a/src/soc/intel/quark/romstage/romstage.c
+++ b/src/soc/intel/quark/romstage/romstage.c
@@ -13,9 +13,12 @@
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
  */
+#define __SIMPLE_DEVICE__
 
 #include <arch/early_variables.h>
 #include <console/console.h>
+#include <cbfs.h>
+#include "../chip.h"
 #include <device/pci_def.h>
 #include <fsp/car.h>
 #include <fsp/util.h>
@@ -47,3 +50,54 @@ struct chipset_power_state *fill_power_state(void)
 	printk(BIOS_DEBUG, "prev_sleep_state %d\n", ps->prev_sleep_state);
 	return ps;
 }
+
+/* Initialize the UPD parameters for MemoryInit */
+void soc_memory_init_params(struct romstage_params *params,
+			    MEMORY_INIT_UPD *upd)
+{
+	const struct device *dev;
+	char *pdat_file;
+	size_t pdat_file_len;
+	const struct soc_intel_quark_config *config;
+
+	/* Locate the pdat.bin file */
+	pdat_file = cbfs_boot_map_with_leak("pdat.bin", CBFS_TYPE_RAW,
+		&pdat_file_len);
+	if (!pdat_file) {
+		printk(BIOS_DEBUG,
+			"Platform configuration file (pdat.bin) not found.");
+		pdat_file_len = 0;
+	}
+
+	/* Locate the configuration data from devicetree.cb */
+	dev = dev_find_slot(0, LPC_DEV_FUNC);
+	if (!dev) {
+		printk(BIOS_ERR,
+			"Error! Device (PCI:0:%02x.%01x) not found, "
+			"soc_memory_init_params!\n", PCI_DEVICE_NUMBER_QNC_LPC,
+			PCI_FUNCTION_NUMBER_QNC_LPC);
+		return;
+	}
+	config = dev->chip_info;
+
+	/* Set the parameters for MemoryInit */
+	printk(BIOS_DEBUG, "Updating UPD values for MemoryInit\n");
+	upd->PcdSmmTsegSize = IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) ?
+		config->PcdSmmTsegSize : 0;
+	upd->PcdPlatformDataBaseAddress = (UINT32)pdat_file;
+	upd->PcdPlatformDataMaxLen = (UINT32)pdat_file_len;
+}
+
+void soc_display_memory_init_params(const MEMORY_INIT_UPD *old,
+	MEMORY_INIT_UPD *new)
+{
+	/* Display the parameters for MemoryInit */
+	printk(BIOS_SPEW, "UPD values for MemoryInit:\n");
+	fsp_display_upd_value("PcdSmmTsegSize", 2,
+		old->PcdSmmTsegSize, new->PcdSmmTsegSize);
+	fsp_display_upd_value("PcdPlatformDataBaseAddress", 4,
+		old->PcdPlatformDataBaseAddress,
+		new->PcdPlatformDataBaseAddress);
+	fsp_display_upd_value("PcdPlatformDataMaxLen", 4,
+		old->PcdPlatformDataMaxLen, new->PcdPlatformDataMaxLen);
+}