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| author | Lee Leahy <leroy.p.leahy@intel.com> | 2016-07-31 17:20:30 -0700 |
|---|---|---|
| committer | Lee Leahy <leroy.p.leahy@intel.com> | 2016-08-05 01:55:17 +0200 |
| commit | f74ce24de1c19cd021c9a09765f024a23c1fc238 (patch) | |
| tree | e3a2186554fbbab5a8cafc83a1eabd2eee8a5f49 /src/soc/intel/quark/romstage | |
| parent | d52636113aa2ff7da27f710db9b8a53ac5de6ed2 (diff) | |
| download | coreboot-f74ce24de1c19cd021c9a09765f024a23c1fc238.tar.xz | |
soc/intel/quark: Clean up debug output levels
Change the debug output levels for quark:
* Remove excess debug output
* Change BIOS_DEBUG to BIOS_SPEW - exception in report_platform.c
TEST=Build and run on Galileo Gen2
Change-Id: I37d7ed21a7fc4c92efeb5b71dd01922d7d4b9192
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/16006
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src/soc/intel/quark/romstage')
| -rw-r--r-- | src/soc/intel/quark/romstage/pcie.c | 3 | ||||
| -rw-r--r-- | src/soc/intel/quark/romstage/romstage.c | 5 |
2 files changed, 0 insertions, 8 deletions
diff --git a/src/soc/intel/quark/romstage/pcie.c b/src/soc/intel/quark/romstage/pcie.c index f2adc18e86..24dcf23ffb 100644 --- a/src/soc/intel/quark/romstage/pcie.c +++ b/src/soc/intel/quark/romstage/pcie.c @@ -100,10 +100,7 @@ static const struct reg_script pcie_bus_init_script[] = { void pcie_init(void) { /* Initialize the PCIe bridges */ - printk(BIOS_DEBUG, "Initializing PCIe controllers\n"); reg_script_run(pcie_init_script); - printk(BIOS_DEBUG, "Initializing PCIe bus 0\n"); reg_script_run_on_dev(PCIE_PORT0_BDF, pcie_bus_init_script); - printk(BIOS_DEBUG, "Initializing PCIe bus 1\n"); reg_script_run_on_dev(PCIE_PORT1_BDF, pcie_bus_init_script); } diff --git a/src/soc/intel/quark/romstage/romstage.c b/src/soc/intel/quark/romstage/romstage.c index 9ee41350e8..e774993bf2 100644 --- a/src/soc/intel/quark/romstage/romstage.c +++ b/src/soc/intel/quark/romstage/romstage.c @@ -18,7 +18,6 @@ #include <arch/early_variables.h> #include <console/console.h> #include <fsp/util.h> -#include <lib.h> #include <soc/pci_devs.h> #include <soc/pm.h> #include <soc/romstage.h> @@ -53,7 +52,6 @@ void disable_rom_shadow(void) /* Determine if the shadow ROM is enabled */ data = port_reg_read(QUARK_NC_HOST_BRIDGE_SB_PORT_ID, QNC_MSG_FSBIC_REG_HMISC); - printk(BIOS_DEBUG, "0x%08x: HMISC\n", data); if ((data & (ESEG_RD_DRAM | FSEG_RD_DRAM)) != (ESEG_RD_DRAM | FSEG_RD_DRAM)) { @@ -62,7 +60,4 @@ void disable_rom_shadow(void) port_reg_write(QUARK_NC_HOST_BRIDGE_SB_PORT_ID, QNC_MSG_FSBIC_REG_HMISC, data); } - - /* Display the DRAM data */ - hexdump((void *)0x000ffff0, 0x10); } |