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authorLee Leahy <leroy.p.leahy@intel.com>2016-12-28 11:43:10 -0800
committerLee Leahy <leroy.p.leahy@intel.com>2017-01-03 21:04:42 +0100
commita765090f0d2f77cb099a60c23da8acaff62cb171 (patch)
tree1ea5e703e4d9c91a2478f06c166bb3e89679f448 /src/soc/intel/quark/romstage
parent73f6a282a191c39d8f5e72e6cd2ce172821cdef4 (diff)
downloadcoreboot-a765090f0d2f77cb099a60c23da8acaff62cb171.tar.xz
soc/intel/quark: Add early debugging code
Add Kconfig values and early debugging code to better segment and debug the early code in bootblock by using the SD LED as an indicator. Update the help text for the debug Kconfig values to point to the various failure locations. TEST=Build and run on Galileo Gen2 Change-Id: I1cd62eba3e9547cb1dd7f547aaec5d4827e14633 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/17985 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/soc/intel/quark/romstage')
-rw-r--r--src/soc/intel/quark/romstage/fsp1_1.c4
1 files changed, 4 insertions, 0 deletions
diff --git a/src/soc/intel/quark/romstage/fsp1_1.c b/src/soc/intel/quark/romstage/fsp1_1.c
index d7f19a74f5..e93e688ea7 100644
--- a/src/soc/intel/quark/romstage/fsp1_1.c
+++ b/src/soc/intel/quark/romstage/fsp1_1.c
@@ -26,6 +26,8 @@
#include <soc/romstage.h>
#include <string.h>
+extern void asmlinkage light_sd_led(void);
+
asmlinkage void *car_stage_c_entry(void)
{
FSP_INFO_HEADER *fih;
@@ -40,6 +42,8 @@ asmlinkage void *car_stage_c_entry(void)
/* Locate the FSP header in ESRAM */
fih = find_fsp(CONFIG_FSP_ESRAM_LOC);
+ if (IS_ENABLED(CONFIG_ENABLE_DEBUG_LED_FINDFSP))
+ light_sd_led();
/* Start the early verstage/romstage code */
post_code(0x2A);