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author | Lee Leahy <leroy.p.leahy@intel.com> | 2016-02-07 14:37:13 -0800 |
---|---|---|
committer | Martin Roth <martinroth@google.com> | 2016-02-09 16:20:38 +0100 |
commit | 87df8d08d676f79b894da84ebe6f8a57f69ba5b1 (patch) | |
tree | c631ba642e44184808868342efd8055ec30731aa /src/soc/intel/quark/romstage | |
parent | 5d7df71cfe6c5a4c8615f33d194cb34947f53c05 (diff) | |
download | coreboot-87df8d08d676f79b894da84ebe6f8a57f69ba5b1.tar.xz |
soc/intel/quark: Enable Serial Port
Add the code to enable debug serial output using HSUART1:
* Enable the code using Kconfig value ENABLE_BUILTIN_HSUART1
* Note that the BIST value is always zero as validated in
esram_init.inc
* The initial TSC value is currently not saved!
Testing on Galileo:
* Edit the src/mainboard/intel/galileo/Makefile.inc file
* Add "select ADD_FSP_PDAT_FILE"
* Add "select ADD_FSP_RAW_BIN"
* Add "select ADD_RMU_FILE"
* Place the FSP.bin file in the location specified by CONFIG_FSP_FILE
* Place the pdat.bin files in the location specified by
CONFIG_FSP_PDAT_FILE
* Place the rmu.bin file in the location specified by CONFIG_RMU_FILE
* Testing is successful if serial output is present on HSUART1 at
115200 baud, 8-bit, no parity
Change-Id: I7e6181e8b9bc901c3ab236f0b56534850bb6bfd0
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/13445
Tested-by: build bot (Jenkins)
Reviewed-by: FEI WANG <wangfei.jimei@gmail.com>
Diffstat (limited to 'src/soc/intel/quark/romstage')
-rw-r--r-- | src/soc/intel/quark/romstage/Makefile.inc | 3 | ||||
-rw-r--r-- | src/soc/intel/quark/romstage/cache_as_ram.inc | 41 | ||||
-rw-r--r-- | src/soc/intel/quark/romstage/romstage.c | 27 | ||||
-rw-r--r-- | src/soc/intel/quark/romstage/uart.c | 42 |
4 files changed, 112 insertions, 1 deletions
diff --git a/src/soc/intel/quark/romstage/Makefile.inc b/src/soc/intel/quark/romstage/Makefile.inc index cb17d3d155..6ade32de69 100644 --- a/src/soc/intel/quark/romstage/Makefile.inc +++ b/src/soc/intel/quark/romstage/Makefile.inc @@ -15,3 +15,6 @@ cpu_incs-y += $(src)/soc/intel/quark/romstage/esram_init.inc cpu_incs-y += $(src)/soc/intel/quark/romstage/cache_as_ram.inc + +romstage-y += romstage.c +romstage-$(CONFIG_ENABLE_BUILTIN_HSUART1) += uart.c diff --git a/src/soc/intel/quark/romstage/cache_as_ram.inc b/src/soc/intel/quark/romstage/cache_as_ram.inc index d323f03b51..4fc60e284b 100644 --- a/src/soc/intel/quark/romstage/cache_as_ram.inc +++ b/src/soc/intel/quark/romstage/cache_as_ram.inc @@ -115,7 +115,46 @@ CAR_init_done: #endif /* CONFIG_ENABLE_DEBUG_LED_TEMPRAMINIT */ /* Set up bootloader stack */ - clrl %eax + movl %edx, %esp + + /* + * eax: 0 + * ebp: FSP_INFO_HEADER address + * ecx: Temp RAM base + * edx: Temp RAM top + * edi: BIST value + * esp: Top of stack in temp RAM + */ + + /* Create cache_as_ram_params on stack */ + pushl %edx /* bootloader CAR end */ + pushl %ecx /* bootloader CAR begin */ + pushl %ebp /* FSP_INFO_HEADER */ + pushl $0 /* BIST - esram_init.inc catches non-zero BIST values */ + /* TODO: Locate 64-bits of storage for initial TSC value */ + pushl $0 /* tsc[63:32] */ + pushl $0 /* tsc[31:0] */ + pushl %esp /* pointer to cache_as_ram_params */ + + /* Save FSP_INFO_HEADER location in ebx */ + mov %ebp, %ebx + + /* Coreboot assumes stack/heap region will be zero */ + cld + movl %ecx, %edi + neg %ecx + /* Only clear up to current stack value. */ + add %esp, %ecx + shrl $2, %ecx + xorl %eax, %eax + rep stosl + +before_romstage: + post_code(0x2A) + + /* Call cache_as_ram_main(struct cache_as_ram_params *) */ + call cache_as_ram_main + movb $0x69, %ah jmp .Lhlt halt1: diff --git a/src/soc/intel/quark/romstage/romstage.c b/src/soc/intel/quark/romstage/romstage.c new file mode 100644 index 0000000000..0951b81424 --- /dev/null +++ b/src/soc/intel/quark/romstage/romstage.c @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015-2016 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <fsp/car.h> +#include <soc/iomap.h> +#include <soc/pci_devs.h> +#include <soc/romstage.h> + +void car_soc_pre_console_init(void) +{ + if (IS_ENABLED(CONFIG_ENABLE_BUILTIN_HSUART1)) + set_base_address_and_enable_uart(0, HSUART1_DEV, HSUART1_FUNC, + UART_BASE_ADDRESS); +} diff --git a/src/soc/intel/quark/romstage/uart.c b/src/soc/intel/quark/romstage/uart.c new file mode 100644 index 0000000000..2d53a48834 --- /dev/null +++ b/src/soc/intel/quark/romstage/uart.c @@ -0,0 +1,42 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2003 Eric Biederman + * Copyright (C) 2006-2010 coresystems GmbH + * Copyright (C) 2015-2016 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +// Use simple device model for this file even in ramstage +#define __SIMPLE_DEVICE__ + +#include <device/pci.h> +#include <device/pci_def.h> +#include <rules.h> +#include <soc/romstage.h> + +int set_base_address_and_enable_uart(u8 bus, u8 dev, u8 func, u32 mmio_base) +{ + uint16_t reg16; + + /* HSUART controller #1 (B0:D20:F5). */ + device_t uart_dev = PCI_DEV(bus, dev, func); + + /* Decode BAR0(offset 0x10). */ + pci_write_config32(uart_dev, PCI_BASE_ADDRESS_0, mmio_base); + + /* Enable MEMBASE at CMD(offset 0x04). */ + reg16 = pci_read_config16(uart_dev, PCI_COMMAND); + reg16 |= PCI_COMMAND_MEMORY; + pci_write_config16(uart_dev, PCI_COMMAND, reg16); + + return 0; +} |