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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-08-17 20:51:08 +0300 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-08-26 21:08:41 +0000 |
| commit | cd7a70f4879ff6e0f3e334ddf1031ccf0c0d31cf (patch) | |
| tree | b0438431df0943ab5f0fa9d80a99fc265130ac23 /src/soc/intel/quark | |
| parent | 16248e89ecf73a76e5d9e9e2de46146f7ffece88 (diff) | |
| download | coreboot-cd7a70f4879ff6e0f3e334ddf1031ccf0c0d31cf.tar.xz | |
soc/intel: Use common romstage code
This provides stack guards with checking and common
entry into postcar.
The code in cpu/intel/car/romstage.c is candidate
for becoming architectural so function prototype
is moved to <arch/romstage.h>.
Change-Id: I4c5a9789e7cf3f7f49a4a33e21dac894320a9639
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34893
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/quark')
| -rw-r--r-- | src/soc/intel/quark/romstage/fsp2_0.c | 26 |
1 files changed, 15 insertions, 11 deletions
diff --git a/src/soc/intel/quark/romstage/fsp2_0.c b/src/soc/intel/quark/romstage/fsp2_0.c index 0489621045..bd30271d77 100644 --- a/src/soc/intel/quark/romstage/fsp2_0.c +++ b/src/soc/intel/quark/romstage/fsp2_0.c @@ -28,12 +28,11 @@ #include <soc/reg_access.h> #include <soc/storage_test.h> +static struct postcar_frame early_mtrrs; + asmlinkage void car_stage_c_entry(void) { - struct postcar_frame pcf; bool s3wake; - uintptr_t top_of_ram; - uintptr_t top_of_low_usable_memory; post_code(0x20); console_init(); @@ -63,28 +62,33 @@ asmlinkage void car_stage_c_entry(void) /* Initialize the PCIe bridges */ pcie_init(); - if (postcar_frame_init(&pcf, 0)) - die("Unable to initialize postcar frame.\n"); + prepare_and_run_postcar(&early_mtrrs); + /* We do not return here. */ +} + +void fill_postcar_frame(struct postcar_frame *pcf) +{ + uintptr_t top_of_ram; + uintptr_t top_of_low_usable_memory; /* Locate the top of RAM */ top_of_low_usable_memory = (uintptr_t) cbmem_top(); top_of_ram = ALIGN(top_of_low_usable_memory, 16 * MiB); /* Cache postcar and ramstage */ - postcar_frame_add_mtrr(&pcf, top_of_ram - (16 * MiB), 16 * MiB, + postcar_frame_add_mtrr(pcf, top_of_ram - (16 * MiB), 16 * MiB, MTRR_TYPE_WRBACK); /* Cache RMU area */ - postcar_frame_add_mtrr(&pcf, (uintptr_t) top_of_low_usable_memory, + postcar_frame_add_mtrr(pcf, (uintptr_t) top_of_low_usable_memory, 0x10000, MTRR_TYPE_WRTHROUGH); /* Cache ESRAM */ - postcar_frame_add_mtrr(&pcf, 0x80000000, 0x80000, MTRR_TYPE_WRBACK); + postcar_frame_add_mtrr(pcf, 0x80000000, 0x80000, MTRR_TYPE_WRBACK); + pcf->skip_common_mtrr = 1; /* Cache SPI flash - Write protect not supported */ - postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRTHROUGH); - - run_postcar_phase(&pcf); + postcar_frame_add_romcache(pcf, MTRR_TYPE_WRTHROUGH); } static struct chipset_power_state power_state; |