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authorLee Leahy <leroy.p.leahy@intel.com>2016-05-22 09:23:49 -0700
committerLeroy P Leahy <leroy.p.leahy@intel.com>2016-05-23 20:43:44 +0200
commitf8841120b2627a25fcc57b67662f727f9c20941e (patch)
tree511ad1c2bb1b0e8183e130b7669bd28fb4ac44af /src/soc/intel/quark
parent6923e8c40d7ac118b578249cf357ff8ac45652f4 (diff)
downloadcoreboot-f8841120b2627a25fcc57b67662f727f9c20941e.tar.xz
soc/intel/quark: Add EHCI errata
Move the EHCI errata from QuarkFSP into coreboot. TEST=Build and run on Galileo Gen2 Change-Id: I424ffd81643fbba9c820b5a8a6809b9412965f8d Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/14940 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@google.com>
Diffstat (limited to 'src/soc/intel/quark')
-rw-r--r--src/soc/intel/quark/ehci.c13
1 files changed, 13 insertions, 0 deletions
diff --git a/src/soc/intel/quark/ehci.c b/src/soc/intel/quark/ehci.c
index 460ef23a79..ed9112ca10 100644
--- a/src/soc/intel/quark/ehci.c
+++ b/src/soc/intel/quark/ehci.c
@@ -24,12 +24,25 @@
#define USB2_PLL2 0x7F03
#define USB2_COMPBG 0x7F04
+/* EHCI Packet Buffer OUT/IN Thresholds, values in number of DWORDs */
+#define EHCI_OUT_THRESHOLD_VALUE 0x7f
+#define EHCI_IN_THRESHOLD_VALUE 0x7f
+
/* In order to configure the USB PHY to use clk120 (ickusbcoreclk) as PLL
* reference clock and Port2 as a USB device port, the following sequence must
* be followed
*/
static const struct reg_script init_script[] = {
+ /* Set packet buffer OUT/IN thresholds */
+ REG_MMIO_RMW32(R_IOH_EHCI_INSNREG01,
+ ~(B_IOH_EHCI_INSNREG01_OUT_THRESHOLD_MASK
+ | B_IOH_EHCI_INSNREG01_IN_THRESHOLD_MASK),
+ (EHCI_OUT_THRESHOLD_VALUE
+ << B_IOH_EHCI_INSNREG01_OUT_THRESHOLD_BP)
+ | (EHCI_IN_THRESHOLD_VALUE
+ << B_IOH_EHCI_INSNREG01_IN_THRESHOLD_BP)),
+
/* Sighting #4930631 PDNRESCFG [8:7] of USB2_GLOBAL_PORT = 11b.
* For port 0 & 1 as host and port 2 as device.
*/