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authorLee Leahy <leroy.p.leahy@intel.com>2016-05-22 07:50:27 -0700
committerLeroy P Leahy <leroy.p.leahy@intel.com>2016-05-23 20:34:07 +0200
commite1bff02ebedf99bbcd331bbd73965bb0c8054e61 (patch)
treeef3473c2be1d5f10e0ed77bb4fd27174917b7896 /src/soc/intel/quark
parent9f444c351c735d3cb82bdd732ff276ce6100c56f (diff)
downloadcoreboot-e1bff02ebedf99bbcd331bbd73965bb0c8054e61.tar.xz
soc/intel/quark: Switch reference from uart_dev to uart_bdf
Switch from using uart_dev to uart_bdf to better describe the value in use. TEST=Build and run on Galileo Gen2 Change-Id: If5066b93ea8ccce4a5b89ee3984c7413d5358e71 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/14938 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@google.com>
Diffstat (limited to 'src/soc/intel/quark')
-rw-r--r--src/soc/intel/quark/romstage/uart.c8
1 files changed, 4 insertions, 4 deletions
diff --git a/src/soc/intel/quark/romstage/uart.c b/src/soc/intel/quark/romstage/uart.c
index 2d53a48834..9e8f6c529b 100644
--- a/src/soc/intel/quark/romstage/uart.c
+++ b/src/soc/intel/quark/romstage/uart.c
@@ -28,15 +28,15 @@ int set_base_address_and_enable_uart(u8 bus, u8 dev, u8 func, u32 mmio_base)
uint16_t reg16;
/* HSUART controller #1 (B0:D20:F5). */
- device_t uart_dev = PCI_DEV(bus, dev, func);
+ pci_devfn_t uart_bdf = PCI_DEV(bus, dev, func);
/* Decode BAR0(offset 0x10). */
- pci_write_config32(uart_dev, PCI_BASE_ADDRESS_0, mmio_base);
+ pci_write_config32(uart_bdf, PCI_BASE_ADDRESS_0, mmio_base);
/* Enable MEMBASE at CMD(offset 0x04). */
- reg16 = pci_read_config16(uart_dev, PCI_COMMAND);
+ reg16 = pci_read_config16(uart_bdf, PCI_COMMAND);
reg16 |= PCI_COMMAND_MEMORY;
- pci_write_config16(uart_dev, PCI_COMMAND, reg16);
+ pci_write_config16(uart_bdf, PCI_COMMAND, reg16);
return 0;
}