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authorKyösti Mälkki <kyosti.malkki@gmail.com>2019-02-12 14:16:21 +0200
committerPatrick Georgi <pgeorgi@google.com>2019-02-27 11:10:00 +0000
commite613d704d12592dfc371d81957a3d83b0742fa7d (patch)
treeb21785796ec4446f1c18c74526e22a97b5cd7318 /src/soc/intel/quark
parent7132f259bf83f1118893550c0bc914c11081ea84 (diff)
downloadcoreboot-e613d704d12592dfc371d81957a3d83b0742fa7d.tar.xz
console: Split loglevel for fast and slow
For fast CBMEM console use minimum BIOS_DEBUG level. For other consoles, Kconfig and/or nvram settings apply. Change-Id: Iff56a0a3182f258200cac80e013957d598cc2130 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/31370 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
Diffstat (limited to 'src/soc/intel/quark')
-rw-r--r--src/soc/intel/quark/romstage/fsp2_0.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/intel/quark/romstage/fsp2_0.c b/src/soc/intel/quark/romstage/fsp2_0.c
index 23051bde6d..c237da5270 100644
--- a/src/soc/intel/quark/romstage/fsp2_0.c
+++ b/src/soc/intel/quark/romstage/fsp2_0.c
@@ -173,7 +173,7 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *fspm_upd, uint32_t version)
upd->RankMask = config->RankMask;
upd->RmuBaseAddress = (uintptr_t)rmu_data;
upd->RmuLength = rmu_data_len;
- upd->SerialPortWriteChar = console_log_level(BIOS_SPEW)
+ upd->SerialPortWriteChar = !!console_log_level(BIOS_SPEW)
? (uintptr_t)fsp_write_line : 0;
upd->SmmTsegSize = IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) ?
config->SmmTsegSize : 0;