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authorAaron Durbin <adurbin@chromium.org>2016-07-13 23:27:12 -0500
committerAaron Durbin <adurbin@chromium.org>2016-07-15 08:34:58 +0200
commitf1e22d5c39cd341f90463908a6cfe5db4fecacda (patch)
treee84bd1f3cce68c76364ffebb7a45e9993c20ffae /src/soc/intel/quark
parentbf168e740f18da612507c14e6aebcf50d948cbf5 (diff)
downloadcoreboot-f1e22d5c39cd341f90463908a6cfe5db4fecacda.tar.xz
soc/intel/quark: use common Intel ACPI hardware definitions
Transition to using the common Intel ACPI hardware definitions generic ACPI definitions. BUG=chrome-os-partner:54977 Change-Id: I034c083604892a5fa25dff3b50e327e0a885b021 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15683 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Lee Leahy <leroy.p.leahy@intel.com>
Diffstat (limited to 'src/soc/intel/quark')
-rw-r--r--src/soc/intel/quark/include/soc/pm.h6
-rw-r--r--src/soc/intel/quark/romstage/romstage.c4
2 files changed, 3 insertions, 7 deletions
diff --git a/src/soc/intel/quark/include/soc/pm.h b/src/soc/intel/quark/include/soc/pm.h
index f9ae027c48..30d8841e34 100644
--- a/src/soc/intel/quark/include/soc/pm.h
+++ b/src/soc/intel/quark/include/soc/pm.h
@@ -18,11 +18,7 @@
#define _SOC_PM_H_
#include <stdint.h>
-
-/* Generic sleep state types */
-#define SLEEP_STATE_S0 0
-#define SLEEP_STATE_S3 3
-#define SLEEP_STATE_S5 5
+#include <arch/acpi.h>
struct chipset_power_state {
uint32_t prev_sleep_state;
diff --git a/src/soc/intel/quark/romstage/romstage.c b/src/soc/intel/quark/romstage/romstage.c
index 2a4c658745..457c922a96 100644
--- a/src/soc/intel/quark/romstage/romstage.c
+++ b/src/soc/intel/quark/romstage/romstage.c
@@ -117,7 +117,7 @@ struct chipset_power_state *fill_power_state(void)
{
struct chipset_power_state *ps = car_get_var_ptr(&power_state);
- ps->prev_sleep_state = 0;
+ ps->prev_sleep_state = ACPI_S0;
printk(BIOS_DEBUG, "prev_sleep_state %d\n", ps->prev_sleep_state);
return ps;
}
@@ -147,7 +147,7 @@ void soc_memory_init_params(struct romstage_params *params,
hexdump((void *)0x000ffff0, 0x10);
/* Clear SMI and wake events */
- if (ps->prev_sleep_state != 3) {
+ if (ps->prev_sleep_state != ACPI_S3) {
printk(BIOS_SPEW, "Clearing SMI interrupts and wake events\n");
reg_script_run_on_dev(LPC_BDF, clear_smi_and_wake_events);
}