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authorFurquan Shaikh <furquan@chromium.org>2016-10-24 15:27:21 -0700
committerFurquan Shaikh <furquan@google.com>2016-10-26 01:50:45 +0200
commit723a84e2920c8ba52257cf4bf445b23ff01d8754 (patch)
tree86ea0f936ee6e9e16e878976a4ad511e7971ce99 /src/soc/intel/skylake/Kconfig
parentaedbfc8f0917b332e648fe6c4333567bd8e58b0d (diff)
downloadcoreboot-723a84e2920c8ba52257cf4bf445b23ff01d8754.tar.xz
soc/intel/skylake: Use intel common support to write-protect SPI flash
BUG=chrome-os-partner:58896 Change-Id: I281c799a1798f3353d78edd8a6cd16bbe762bc2c Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17116 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src/soc/intel/skylake/Kconfig')
-rw-r--r--src/soc/intel/skylake/Kconfig1
1 files changed, 1 insertions, 0 deletions
diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig
index 5a1d878f90..a5fb0e8d84 100644
--- a/src/soc/intel/skylake/Kconfig
+++ b/src/soc/intel/skylake/Kconfig
@@ -44,6 +44,7 @@ config CPU_SPECIFIC_OPTIONS
select SOC_INTEL_COMMON_LPSS_I2C
select SOC_INTEL_COMMON_NHLT
select SOC_INTEL_COMMON_RESET
+ select SOC_INTEL_COMMON_SPI_PROTECT
select SMM_TSEG
select SMP
select SSE2