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author | Furquan Shaikh <furquan@chromium.org> | 2016-11-21 09:19:53 -0800 |
---|---|---|
committer | Furquan Shaikh <furquan@google.com> | 2016-11-22 17:39:07 +0100 |
commit | d0c00052d32ed2ea461811632197845120ca8a08 (patch) | |
tree | 03c311038a65edb62bfe6a763a4667a5af408239 /src/soc/intel/skylake/Kconfig | |
parent | d2fb6ae813880b8fd1b3983e0e61c7e51fb9b20b (diff) | |
download | coreboot-d0c00052d32ed2ea461811632197845120ca8a08.tar.xz |
soc/intel: Use correct terminology for SPI flash operations
FPR is an attribute of the SPI flash component and not of the SPI bus
itself. Rename functions, file names and Kconfig option to make sure
this is conveyed correctly.
BUG=None
BRANCH=None
TEST=Compiles successfully.
Change-Id: I9f06f1a8ee28b8c56db64ddd6a19dd9179c54f50
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17560
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/skylake/Kconfig')
-rw-r--r-- | src/soc/intel/skylake/Kconfig | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index 04dbf0e1fb..988547c8a8 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -44,7 +44,7 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_LPSS_I2C select SOC_INTEL_COMMON_NHLT select SOC_INTEL_COMMON_RESET - select SOC_INTEL_COMMON_SPI_PROTECT + select SOC_INTEL_COMMON_SPI_FLASH_PROTECT select SMM_TSEG select SMP select SSE2 |