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authorAaron Durbin <adurbin@chromium.org>2016-08-11 23:55:39 -0500
committerMartin Roth <martinroth@google.com>2016-08-19 18:15:50 +0200
commite4cc8cd00b3b39eecac604cc402b8111f8fd5657 (patch)
tree05a7dd628ff2f307c8b519739edb0bee2509d1e8 /src/soc/intel/skylake/Kconfig
parent7b2c781dbdb226af1db10547500be91f45ee8cc0 (diff)
downloadcoreboot-e4cc8cd00b3b39eecac604cc402b8111f8fd5657.tar.xz
soc/intel/skylake: use SPI flash boot_device_rw() for ealy stages
If the boot device is SPI flash use the common one in the early stages. While tweaking the config don't auto select SPI_FLASH as that is handled automatically by the rest of the build system. BUG=chrome-os-partner:56151 Change-Id: Ifd51a80fd008c336233d6e460c354190fcc0ef22 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16202 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc/intel/skylake/Kconfig')
-rw-r--r--src/soc/intel/skylake/Kconfig2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig
index a61774f0a4..7fa129bf18 100644
--- a/src/soc/intel/skylake/Kconfig
+++ b/src/soc/intel/skylake/Kconfig
@@ -13,6 +13,7 @@ config CPU_SPECIFIC_OPTIONS
select ARCH_ROMSTAGE_X86_32
select ARCH_VERSTAGE_X86_32
select ACPI_NHLT
+ select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH
select BOOT_DEVICE_SUPPORTS_WRITES
select CACHE_MRC_SETTINGS
select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM if RELOCATABLE_RAMSTAGE
@@ -46,7 +47,6 @@ config CPU_SPECIFIC_OPTIONS
select SOC_INTEL_COMMON_RESET
select SMM_TSEG
select SMP
- select SPI_FLASH
select SSE2
select SUPPORT_CPU_UCODE_IN_CBFS
select TSC_CONSTANT_RATE