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| author | Subrata Banik <subrata.banik@intel.com> | 2017-08-14 11:55:10 +0530 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-08-21 16:13:10 +0000 |
| commit | 19a7adeffe5a9d50fec9cb4ab81a7d40ce387f08 (patch) | |
| tree | 53d7a05e1b6329000a648bdbc42a378bff9d7c01 /src/soc/intel/skylake/Kconfig | |
| parent | d6bd825d6c584d38bb69e5c4cccae4255837f359 (diff) | |
| download | coreboot-19a7adeffe5a9d50fec9cb4ab81a7d40ce387f08.tar.xz | |
soc/intel/skylake: Add Kconfig option to select UART index
Skylake/Kabylake SOC has two possible ways to make serial
console functional.
1. Legacy IO based access using Port 0x3F8.
2. LPSS UART PCI based access.
This patch to provide option to select index for LPSS
UART port: 0 = LPSS UART0, 1 = LPSS UART1, 2 = LPSS UART2
PCI based LPSS UART2 is by default enabled for Chrome Design.
Change-Id: I9647820fe59b5d1a1001a611b9ae3580946da0ae
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/20996
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/skylake/Kconfig')
| -rw-r--r-- | src/soc/intel/skylake/Kconfig | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index f0402a9e2b..7a3c3a6995 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -200,6 +200,13 @@ config UART_DEBUG select DRIVERS_UART_8250MEM_32 select NO_UART_ON_SUPERIO +config UART_FOR_CONSOLE + int "Index for LPSS UART port to use for console" + default 2 if DRIVERS_UART_8250MEM + help + Index for LPSS UART port to use for console: + 0 = LPSS UART0, 1 = LPSS UART1, 2 = LPSS UART2 + config SKYLAKE_SOC_PCH_H bool default n |