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authorNico Huber <nico.h@gmx.de>2019-05-29 23:33:06 +0200
committerNico Huber <nico.h@gmx.de>2019-06-03 15:23:49 +0000
commit9995418166bc4074de2a99aa50e74f8a88196c39 (patch)
treeaf67d06bed637d45d36ec9fc089c4974e536e682 /src/soc/intel/skylake/Kconfig
parent10ed374d7d6555992a7434370130d813bfa3ad89 (diff)
downloadcoreboot-9995418166bc4074de2a99aa50e74f8a88196c39.tar.xz
soc/intel: Replace UART_BASE() and friends with a Kconfig
Re-add the Kconfig CONSOLE_UART_BASE_ADDRESS. It was lost by accident on APL at least. It is used outside of soc/intel/ scope, e.g. to con- figure SeaBIOS. As we only ever configure a single UART for the coreboot console, we don't need different addresses for each possible UART. Which saves us a lot of code. Change-Id: I28e1d98aa37a6acb57b98b8882fc4fa131d5d309 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33098 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Diffstat (limited to 'src/soc/intel/skylake/Kconfig')
-rw-r--r--src/soc/intel/skylake/Kconfig5
1 files changed, 5 insertions, 0 deletions
diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig
index fcfe2b6591..626b5f80f0 100644
--- a/src/soc/intel/skylake/Kconfig
+++ b/src/soc/intel/skylake/Kconfig
@@ -289,6 +289,11 @@ config CPU_BCLK_MHZ
int
default 100
+config CONSOLE_UART_BASE_ADDRESS
+ hex
+ default 0xfe030000
+ depends on INTEL_LPSS_UART_FOR_CONSOLE
+
# Clock divider parameters for 115200 baud rate
config SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL
hex