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| author | Subrata Banik <subrata.banik@intel.com> | 2018-05-09 14:55:09 +0530 |
|---|---|---|
| committer | Subrata Banik <subrata.banik@intel.com> | 2018-06-06 06:23:45 +0000 |
| commit | c4986eb7f4eee0f305c6a6f05b45effae152062c (patch) | |
| tree | 46185566d98e49bbfa60acfdedc60e1e423823d3 /src/soc/intel/skylake/Kconfig | |
| parent | f513cebd8b966c15e3c8abcd2d0f540607ea5964 (diff) | |
| download | coreboot-c4986eb7f4eee0f305c6a6f05b45effae152062c.tar.xz | |
soc/intel/common/block: Add common chip config block
Adding common chip config structure which will be used to return data to
common code. When common code requires soc data, code used to fetch
entire soc config structure. With this change, common code will only get
the data/structure which is required by common code and not entire
config.
For now, adding i2c, gspi and lockdown configuration which will be used
by common code.
BUG=none
BRANCH=b:78109109
TEST=compile code for APL/SKL/CNL. Boot using SKL/APL/CNL and check
values are returned properly using common structure.
Change-Id: I7f1671e064782397d3ace066a08bf1333192b21a
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/26189
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Hannah Williams <hannah.williams@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/skylake/Kconfig')
| -rw-r--r-- | src/soc/intel/skylake/Kconfig | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index bfaa19f5d6..13b18dc151 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -56,6 +56,7 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE select SOC_INTEL_COMMON_BLOCK + select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG select SOC_INTEL_COMMON_BLOCK_CPU select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT select SOC_INTEL_COMMON_BLOCK_GPIO_LEGACY_MACROS @@ -329,6 +330,10 @@ config SOC_INTEL_COMMON_BLOCK_GSPI_MAX int default 2 +config SOC_INTEL_I2C_DEV_MAX + int + default 6 + config CPU_BCLK_MHZ int default 100 |