soc/intel/skylake: use postcar stage for fsp 2.0

Utilize the postcar stage for tearing down CAR and initializing
the MTRRs once ram is up. This flow is consistent with apollolake
and allows CAR_GLOBAL variables to be directly accessed and no
need for migrating CAR_GLOBAL variables as romstage doesn't
run with and without CAR being available.

Change-Id: I76de447710ae1d405886eb9420dc4064aa26eccc
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/19335
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>

1 files changed, 5 insertions, 0 deletions

diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc
index 2ef4bba143..171a9165e5 100644
--- a/src/soc/intel/skylake/Makefile.inc
+++ b/src/soc/intel/skylake/Makefile.inc
@@ -103,6 +103,11 @@ smm-$(CONFIG_SPI_FLASH_SMM) += spi.c
 smm-y += tsc_freq.c
 smm-$(CONFIG_UART_DEBUG) += uart_debug.c
 
+postcar-y += memmap.c
+postcar-y += monotonic_timer.c
+postcar-y += tsc_freq.c
+postcar-$(CONFIG_UART_DEBUG) += uart_debug.c
+
 # cpu_microcode_bins += ???
 
 CPPFLAGS_common += -I$(src)/soc/intel/skylake