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authorMichael Niewöhner <foss@mniewoehner.de>2019-10-19 15:17:06 +0200
committerNico Huber <nico.h@gmx.de>2019-11-04 19:24:49 +0000
commite75a64f822931a5fbdd80f20c4d168a5c346e01a (patch)
treebe951bed3220dac1d7a9fc34c8e534da53f55311 /src/soc/intel/skylake/Makefile.inc
parent68da45479fd289281017768a8cfa51b2f642ac07 (diff)
downloadcoreboot-e75a64f822931a5fbdd80f20c4d168a5c346e01a.tar.xz
soc/intel: skl,cnl,icl: consolidate ebda and memmap
As of CB:36136 ebda and memmap are identical for skl, cnl and icl, thus move them to common code. Tested successfully on X11SSM-F Change-Id: I9a20c814d2a6874fcb4ff99ef1a7825d891f74e2 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36137 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/skylake/Makefile.inc')
-rw-r--r--src/soc/intel/skylake/Makefile.inc3
1 files changed, 0 insertions, 3 deletions
diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc
index cb0906c1d5..b049e84795 100644
--- a/src/soc/intel/skylake/Makefile.inc
+++ b/src/soc/intel/skylake/Makefile.inc
@@ -33,7 +33,6 @@ verstage-y += uart.c
romstage-y += gpio.c
romstage-y += gspi.c
romstage-y += i2c.c
-romstage-y += memmap.c
romstage-y += me.c
romstage-y += pmc.c
romstage-y += pmutil.c
@@ -54,7 +53,6 @@ ramstage-y += irq.c
ramstage-y += lockdown.c
ramstage-y += lpc.c
ramstage-y += me.c
-ramstage-y += memmap.c
ramstage-y += p2sb.c
ramstage-y += pmc.c
ramstage-y += pmutil.c
@@ -76,7 +74,6 @@ smm-y += smihandler.c
smm-y += uart.c
smm-y += xhci.c
-postcar-y += memmap.c
postcar-y += gspi.c
postcar-y += spi.c
postcar-y += i2c.c