intel/skylake: IRQ programming through UPD

Implemented Device IRQ porgramming, PxRC to IRQ mapping,
GPIO IRQ routing, SCI IRQ select through UPD

BUG=NONE
BRANCH=NONE
CQ-DEPEND=CL:*232948
TEST= build and booted sklrvp,kunimitsu with this changes.

Change-Id: Ic98074491fe5251a48ed55b6fb7ef31809c3abf3
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 534bd65e5df8654d745c8efe491a332336c9cdc3
Original-Change-Id: I4ea6f3cdb15d371c6023bfd046f3475290f5aa26
Original-Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Original-Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/291403
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/12146
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>

1 files changed, 43 insertions, 45 deletions

diff --git a/src/soc/intel/skylake/acpi/pci_irqs.asl b/src/soc/intel/skylake/acpi/pci_irqs.asl
index 3bf5f3e442..1ab6d3efb0 100644
--- a/src/soc/intel/skylake/acpi/pci_irqs.asl
+++ b/src/soc/intel/skylake/acpi/pci_irqs.asl
@@ -19,66 +19,64 @@
  * Foundation, Inc.
  */
 
+#include <soc/interrupt.h>
+#include <soc/irq.h>
+
 Name (PICP, Package () {
 	/* D31: cAVS, SMBus, GbE, Nothpeak */
-	Package () { 0x001FFFFF, 0, 0, 16 },
-	Package () { 0x001FFFFF, 1, 0, 17 },
-	Package () { 0x001FFFFF, 2, 0, 18 },
-	Package () { 0x001FFFFF, 3, 0, 19 },
+	Package () { 0x001FFFFF, 0, 0, cAVS_INTA_IRQ },
+	Package () { 0x001FFFFF, 1, 0, SMBUS_INTB_IRQ },
+	Package () { 0x001FFFFF, 2, 0, GbE_INTC_IRQ },
+	Package () { 0x001FFFFF, 3, 0, TRACE_HUB_INTD_IRQ },
 	/* D30: SerialIo and SCS */
-	Package () { 0x001EFFFF, 0, 0, 20 },
-	Package () { 0x001EFFFF, 1, 0, 21 },
-	Package () { 0x001EFFFF, 2, 0, 22 },
-	Package () { 0x001EFFFF, 3, 0, 23 },
+	Package () { 0x001EFFFF, 0, 0, LPSS_UART0_IRQ },
+	Package () { 0x001EFFFF, 1, 0, eMMC_IRQ },
+	Package () { 0x001EFFFF, 2, 0, SDIO_IRQ },
+	Package () { 0x001EFFFF, 3, 0, SD_IRQ },
 	/* D29: PCI Express Port 9-16 */
-	Package () { 0x001DFFFF, 0, 0, 16 },
-	Package () { 0x001DFFFF, 1, 0, 17 },
-	Package () { 0x001DFFFF, 2, 0, 18 },
-	Package () { 0x001DFFFF, 3, 0, 19 },
+	Package () { 0x001DFFFF, 0, 0, PCIE_9_IRQ },
+	Package () { 0x001DFFFF, 1, 0, PCIE_10_IRQ },
+	Package () { 0x001DFFFF, 2, 0, PCIE_11_IRQ },
+	Package () { 0x001DFFFF, 3, 0, PCIE_12_IRQ },
 	/* D28: PCI Express Port 1-8 */
-	Package () { 0x001CFFFF, 0, 0, 16 },
-	Package () { 0x001CFFFF, 1, 0, 17 },
-	Package () { 0x001CFFFF, 2, 0, 18 },
-	Package () { 0x001CFFFF, 3, 0, 19 },
-	/* D27: PCI Express Port 17-20 */
-	Package () { 0x001BFFFF, 0, 0, 16 },
-	Package () { 0x001BFFFF, 1, 0, 17 },
-	Package () { 0x001BFFFF, 2, 0, 18 },
-	Package () { 0x001BFFFF, 3, 0, 19 },
+	Package () { 0x001CFFFF, 0, 0, PCIE_1_IRQ },
+	Package () { 0x001CFFFF, 1, 0, PCIE_2_IRQ },
+	Package () { 0x001CFFFF, 2, 0, PCIE_3_IRQ },
+	Package () { 0x001CFFFF, 3, 0, PCIE_4_IRQ },
 	/* D25: SerialIo */
-	Package () { 0x0019FFFF, 0, 0, 32 },
-	Package () { 0x0019FFFF, 1, 0, 33 },
-	Package () { 0x0019FFFF, 2, 0, 34 },
+	Package () { 0x0019FFFF, 0, 0, LPSS_UART2_IRQ },
+	Package () { 0x0019FFFF, 1, 0, LPSS_I2C5_IRQ },
+	Package () { 0x0019FFFF, 2, 0, LPSS_I2C4_IRQ },
 	/* D22: CSME (HECI, IDE-R, KT redirection */
-	Package () { 0x0016FFFF, 0, 0, 16 },
-	Package () { 0x0016FFFF, 1, 0, 17 },
-	Package () { 0x0016FFFF, 2, 0, 18 },
-	Package () { 0x0016FFFF, 3, 0, 19 },
+	Package () { 0x0016FFFF, 0, 0, HECI_1_IRQ },
+	Package () { 0x0016FFFF, 1, 0, HECI_2_IRQ },
+	Package () { 0x0016FFFF, 2, 0, IDER_IRQ },
+	Package () { 0x0016FFFF, 3, 0, KT_IRQ },
 	/* D21: SerialIo */
-	Package () { 0x0015FFFF, 0, 0, 16 },
-	Package () { 0x0015FFFF, 1, 0, 17 },
-	Package () { 0x0015FFFF, 2, 0, 18 },
-	Package () { 0x0015FFFF, 3, 0, 19 },
+	Package () { 0x0015FFFF, 0, 0, LPSS_I2C0_IRQ },
+	Package () { 0x0015FFFF, 1, 0, LPSS_I2C1_IRQ },
+	Package () { 0x0015FFFF, 2, 0, LPSS_I2C2_IRQ },
+	Package () { 0x0015FFFF, 3, 0, LPSS_I2C3_IRQ },
 	/* D20: xHCI, OTG, Thermal, Camera */
-	Package () { 0x0014FFFF, 0, 0, 16 },
-	Package () { 0x0014FFFF, 1, 0, 17 },
-	Package () { 0x0014FFFF, 2, 0, 18 },
-	Package () { 0x0014FFFF, 3, 0, 19 },
+	Package () { 0x0014FFFF, 0, 0, XHCI_IRQ },
+	Package () { 0x0014FFFF, 1, 0, OTG_IRQ },
+	Package () { 0x0014FFFF, 2, 0, THRMAL_IRQ },
+	Package () { 0x0014FFFF, 3, 0, CIO_INTD_IRQ },
 	/* D19: Integrated Sensor Hub */
-	Package () { 0x0013FFFF, 0, 0, 20 },
+	Package () { 0x0013FFFF, 0, 0, ISH_IRQ },
 	/* P.E.G. Root Port D1F0 */
-	Package () { 0x0001FFFF, 0, 0, 16 },
-	Package () { 0x0001FFFF, 1, 0, 17 },
-	Package () { 0x0001FFFF, 2, 0, 18 },
-	Package () { 0x0001FFFF, 3, 0, 19 },
+	Package () { 0x0001FFFF, 0, 0, PEG_RP_INTA_IRQ },
+	Package () { 0x0001FFFF, 1, 0, PEG_RP_INTB_IRQ },
+	Package () { 0x0001FFFF, 2, 0, PEG_RP_INTC_IRQ },
+	Package () { 0x0001FFFF, 3, 0, PEG_RP_INTD_IRQ },
 	/* SA IGFX Device */
-	Package () { 0x0002FFFF, 0, 0, 16 },
+	Package () { 0x0002FFFF, 0, 0, IGFX_IRQ },
 	/* SA Thermal Device */
-	Package () { 0x0004FFFF, 0, 0, 16 },
+	Package () { 0x0004FFFF, 0, 0, SA_THERMAL_IRQ },
 	/* SA SkyCam Device */
-	Package () { 0x0005FFFF, 0, 0, 16 },
+	Package () { 0x0005FFFF, 0, 0, SKYCAM_IRQ },
 	/* SA GMM Device */
-	Package () { 0x0008FFFF, 0, 0, 16 },
+	Package () { 0x0008FFFF, 0, 0, GMM_IRQ },
 })
 
 Name (PICN, Package () {