diff options
| author | Hannah Williams <hannah.williams@intel.com> | 2017-04-06 20:54:11 -0700 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2017-10-02 22:32:33 +0000 |
| commit | 1760cd3eb44ad123b6d3e3e295cdbf43f9465db1 (patch) | |
| tree | 25d37433765d4824d41075b39bb7396e9f0a504b /src/soc/intel/skylake/acpi | |
| parent | a05fdcb2695a9d7c553c23ef6c35c37d7cd7b795 (diff) | |
| download | coreboot-1760cd3eb44ad123b6d3e3e295cdbf43f9465db1.tar.xz | |
soc/intel/skylake: Use common/block/gpio
Other than switch to use common gpio implementation for skylake based
platform, also apply the needed changes for purism board.
Change-Id: I06e06dbcb6d0d6fe277dfad57b82aca51f94b099
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/19201
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Youness Alaoui <snifikino@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/skylake/acpi')
| -rw-r--r-- | src/soc/intel/skylake/acpi/gpio.asl | 13 | ||||
| -rw-r--r-- | src/soc/intel/skylake/acpi/pch.asl | 2 |
2 files changed, 9 insertions, 6 deletions
diff --git a/src/soc/intel/skylake/acpi/gpio.asl b/src/soc/intel/skylake/acpi/gpio.asl index fb220959d5..ebf4289218 100644 --- a/src/soc/intel/skylake/acpi/gpio.asl +++ b/src/soc/intel/skylake/acpi/gpio.asl @@ -13,7 +13,10 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ -#include <soc/gpio_defs.h> +#include <soc/gpio.h> + +#define GPIOTXSTATE_MASK 0x1 +#define GPIORXSTATE_MASK 0x1 Device (GPIO) { @@ -51,7 +54,7 @@ Device (GPIO) Store (GPIO_BASE_SIZE, LEN3) CreateDWordField (^RBUF, ^GIRQ._INT, IRQN) - And (^^PCRR (PID_GPIOCOM0, MISCCFG_OFFSET), + And (^^PCRR (PID_GPIOCOM0, GPIO_MISCCFG), GPIO_DRIVER_IRQ_ROUTE_MASK, Local0) If (LEqual (Local0, GPIO_DRIVER_IRQ_ROUTE_IRQ14)) { @@ -115,7 +118,7 @@ Method (GADD, 1, NotSerialized) } #endif /* CONFIG_SKYLAKE_SOC_PCH_H */ Store (PCRB (Local0), Local2) - Add (Local2, PAD_CFG_DW_OFFSET, Local2) + Add (Local2, PAD_CFG_BASE, Local2) Return (Add (Local2, Multiply (Local1, 8))) } @@ -130,7 +133,7 @@ Method (GRXS, 1, Serialized) { VAL0, 32 } - And (GPIORXSTATE_MASK, ShiftRight (VAL0, GPIORXSTATE_SHIFT), Local0) + And (GPIORXSTATE_MASK, ShiftRight (VAL0, PAD_CFG0_RX_STATE_BIT), Local0) Return (Local0) } @@ -146,7 +149,7 @@ Method (GTXS, 1, Serialized) { VAL0, 32 } - And (GPIOTXSTATE_MASK, ShiftRight (VAL0, GPIOTXSTATE_SHIFT), Local0) + And (GPIOTXSTATE_MASK, ShiftRight (VAL0, PAD_CFG0_TX_STATE_BIT), Local0) Return (Local0) } diff --git a/src/soc/intel/skylake/acpi/pch.asl b/src/soc/intel/skylake/acpi/pch.asl index 74cdb9ce8d..03c2570a44 100644 --- a/src/soc/intel/skylake/acpi/pch.asl +++ b/src/soc/intel/skylake/acpi/pch.asl @@ -19,7 +19,7 @@ #include <intelblocks/pcr.h> #include <soc/iomap.h> #include <soc/irq.h> -#include <soc/gpio_defs.h> +#include <soc/itss.h> #include <soc/gpe.h> #include <soc/pcr_ids.h> |