diff options
| author | Naresh G Solanki <naresh.solanki@intel.com> | 2017-03-16 15:30:25 +0530 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-04-07 21:44:29 +0200 |
| commit | fb7937918ae4c52c2c6b9749e3cd3277615e2f6e (patch) | |
| tree | 94b59e6dbbe5cbdff772dfa7b85ec70b1ebb4be4 /src/soc/intel/skylake/acpi | |
| parent | 44ff10eaa6f480067b080138ced567122cb2a000 (diff) | |
| download | coreboot-fb7937918ae4c52c2c6b9749e3cd3277615e2f6e.tar.xz | |
soc/intel/skylake: Enable XHCI clock gate control in ACPI
Enable SS link trunk clock gating & D3hot when device enters
D3 state.
Similarly disable SS link trunk clock gating & D3hot when device enters
D0 state
TEST=Build & boot Poppy board. Check working for XHCI wake when DUT
is in S3.
Change-Id: Ida2afa2e5f9404c0c15d7027480a28a003ad9a40
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Reviewed-on: https://review.coreboot.org/18879
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/skylake/acpi')
| -rw-r--r-- | src/soc/intel/skylake/acpi/xhci.asl | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/src/soc/intel/skylake/acpi/xhci.asl b/src/soc/intel/skylake/acpi/xhci.asl index 96f3b6a6e5..4c6625eb01 100644 --- a/src/soc/intel/skylake/acpi/xhci.asl +++ b/src/soc/intel/skylake/acpi/xhci.asl @@ -93,12 +93,18 @@ Device (XHCI) Offset (0x10), , 16, XMEM, 16, /* MEM_BASE */ + Offset (0x50), /* XHCLKGTEN */ + , 2, + STGE, 1, /* SS Link Trunk clock gating enable */ Offset (0x74), D0D3, 2, /* POWERSTATE */ , 6, PMEE, 1, /* PME_EN */ , 6, PMES, 1, /* PME_STS */ + Offset (0xA2), + , 2, + D3HE, 1, /* D3_hot_en */ } OperationRegion (XREG, SystemMemory, @@ -124,6 +130,10 @@ Device (XHCI) Return } + /* Disable d3hot and SS link trunk clock gating */ + Store(Zero, ^D3HE) + Store(Zero, ^STGE) + /* If device is in D3, set back to D0 */ If (LEqual (^D0D3, 3)) { Store (Zero, Local0) @@ -178,6 +188,10 @@ Device (XHCI) /* Enable USB2 PHY SUS Well Power Gating in D0/D0i2/D0i3/D3 */ Store (3, ^UPSW) + /* Enable d3hot and SS link trunk clock gating */ + Store(One, ^D3HE) + Store(One, ^STGE) + /* Now put device in D3 */ Store (3, Local0) Store (Local0, ^D0D3) |