diff options
author | Lee Leahy <leroy.p.leahy@intel.com> | 2015-05-12 18:23:27 -0700 |
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committer | Leroy P Leahy <leroy.p.leahy@intel.com> | 2015-07-16 17:24:48 +0200 |
commit | 1d14b3e926c15027f9272f1e80b8913fef8cf25d (patch) | |
tree | b3d89ad4bb1b0ea5ac05d1d7dc6cbf26ec93e6c3 /src/soc/intel/skylake/bootblock/pch.c | |
parent | b000513741d330947bb832a5835378e35bdfb394 (diff) | |
download | coreboot-1d14b3e926c15027f9272f1e80b8913fef8cf25d.tar.xz |
soc/intel: Add Skylake SOC support
Add the files to support the Skylake SOC.
Matches chromium tree at 927026db
BRANCH=none
BUG=None
TEST=Build and run on a Skylake platform
Change-Id: I80248f7e47eaf13b52e3c7ff951eb1976edbaa15
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: http://review.coreboot.org/10341
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/skylake/bootblock/pch.c')
-rw-r--r-- | src/soc/intel/skylake/bootblock/pch.c | 47 |
1 files changed, 4 insertions, 43 deletions
diff --git a/src/soc/intel/skylake/bootblock/pch.c b/src/soc/intel/skylake/bootblock/pch.c index 2fa722097c..9f256e3a95 100644 --- a/src/soc/intel/skylake/bootblock/pch.c +++ b/src/soc/intel/skylake/bootblock/pch.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2014 Google Inc. + * Copyright (C) 2015 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -14,14 +15,12 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * Foundation, Inc. */ - #include <arch/io.h> #include <soc/iomap.h> #include <soc/lpc.h> #include <soc/pci_devs.h> -#include <soc/rcba.h> #include <soc/spi.h> /* @@ -29,51 +28,13 @@ */ static void enable_spi_prefetch(void) { - u8 reg8 = pci_read_config8(PCH_DEV_LPC, 0xdc); + u8 reg8 = pci_read_config8(PCH_DEV_SPI, 0xdc); reg8 &= ~(3 << 2); reg8 |= (2 << 2); /* Prefetching and Caching Enabled */ - pci_write_config8(PCH_DEV_LPC, 0xdc, reg8); -} - - -static void map_rcba(void) -{ - pci_write_config32(PCH_DEV_LPC, RCBA, RCBA_BASE_ADDRESS | 1); -} - -static void enable_port80_on_lpc(void) -{ - /* Enable port 80 POST on LPC. The chipset does this by default, - * but it doesn't appear to hurt anything. */ - u32 gcs = RCBA32(GCS); - gcs = gcs & ~0x4; - RCBA32(GCS) = gcs; -} - -static void set_spi_speed(void) -{ - u32 fdod; - u8 ssfc; - - /* Observe SPI Descriptor Component Section 0 */ - SPIBAR32(SPIBAR_FDOC) = 0x1000; - - /* Extract the Write/Erase SPI Frequency from descriptor */ - fdod = SPIBAR32(SPIBAR_FDOD); - fdod >>= 24; - fdod &= 7; - - /* Set Software Sequence frequency to match */ - ssfc = SPIBAR8(SPIBAR_SSFC + 2); - ssfc &= ~7; - ssfc |= fdod; - SPIBAR8(SPIBAR_SSFC + 2) = ssfc; + pci_write_config8(PCH_DEV_SPI, 0xdc, reg8); } static void bootblock_southbridge_init(void) { - map_rcba(); enable_spi_prefetch(); - enable_port80_on_lpc(); - set_spi_speed(); } |