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author | Duncan Laurie <dlaurie@chromium.org> | 2016-10-25 20:03:56 -0700 |
---|---|---|
committer | Duncan Laurie <dlaurie@chromium.org> | 2016-10-27 16:30:36 +0200 |
commit | f0ba2259b84c1f5083dab14925351ddf8b245e11 (patch) | |
tree | bcda19afec97488539f1d52f2c0af936e6ed321b /src/soc/intel/skylake/bootblock/pch.c | |
parent | 64ce1d122c0464a4ef138fb7452a91b408b1a7c2 (diff) | |
download | coreboot-f0ba2259b84c1f5083dab14925351ddf8b245e11.tar.xz |
skylake: Prepare GPE for use in bootblock
Export the pmc_gpe_init() function from pmc.c to pmutil.c
so it can be used in bootblock, and then call it from there
to initialize any GPEs for use in firmware.
BUG=chrome-os-partner:58666
TEST=test working GPE as TPM interrupt on skylake board
Change-Id: I6b4f7d0aa689db42dc455075f84ab5694e8c9661
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/17135
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src/soc/intel/skylake/bootblock/pch.c')
-rw-r--r-- | src/soc/intel/skylake/bootblock/pch.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/soc/intel/skylake/bootblock/pch.c b/src/soc/intel/skylake/bootblock/pch.c index 57b5fedb24..371dd63685 100644 --- a/src/soc/intel/skylake/bootblock/pch.c +++ b/src/soc/intel/skylake/bootblock/pch.c @@ -301,6 +301,9 @@ void pch_early_init(void) /* Program SMBUS_BASE_ADDRESS and Enable it */ enable_smbus(); + /* Set up GPE configuration */ + pmc_gpe_init(); + soc_config_rtc(); enable_heci(); |