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authorBarnali Sarkar <barnali.sarkar@intel.com>2017-03-31 18:11:49 +0530
committerFurquan Shaikh <furquan@google.com>2017-05-02 18:26:07 +0200
commit7146445be9618eb47895782912af28fb627c009d (patch)
treeec95cd0ab17fecd4ce91bb9b6bff459d9459f3f4 /src/soc/intel/skylake/bootblock
parentc261c4b426ac806cca732bb30459f0e6e855828a (diff)
downloadcoreboot-7146445be9618eb47895782912af28fb627c009d.tar.xz
soc/intel/skylake: Clean up code by using common FAST_SPI module
This patch currently contains the following - 1. Use SOC_INTEL_COMMON_BLOCK_FAST_SPI kconfig for common FAST_SPI code. 2. Perform FAST_SPI programming by calling APIs from common FAST_SPI library. 3. Use common FAST_SPI header file. Change-Id: I4fc90504d322db70ed4ea644b1593cc0605b5fe8 Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Reviewed-on: https://review.coreboot.org/19055 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc/intel/skylake/bootblock')
-rw-r--r--src/soc/intel/skylake/bootblock/cpu.c31
-rw-r--r--src/soc/intel/skylake/bootblock/pch.c36
2 files changed, 9 insertions, 58 deletions
diff --git a/src/soc/intel/skylake/bootblock/cpu.c b/src/soc/intel/skylake/bootblock/cpu.c
index fab589f611..040e847e6c 100644
--- a/src/soc/intel/skylake/bootblock/cpu.c
+++ b/src/soc/intel/skylake/bootblock/cpu.c
@@ -14,20 +14,20 @@
* GNU General Public License for more details.
*/
-#include <stdint.h>
-#include <delay.h>
#include <arch/io.h>
#include <console/console.h>
-#include <cpu/x86/mtrr.h>
#include <cpu/intel/microcode/microcode.c>
-#include <reset.h>
+#include <cpu/x86/mtrr.h>
+#include <delay.h>
+#include <intelblocks/fast_spi.h>
#include <lib.h>
+#include <reset.h>
#include <soc/bootblock.h>
#include <soc/cpu.h>
#include <soc/iomap.h>
#include <soc/msr.h>
#include <soc/pci_devs.h>
-#include <soc/spi.h>
+#include <stdint.h>
/* Soft Reset Data Register Bit 12 = MAX Boot Frequency */
#define SPI_STRAP_MAX_FREQ (1<<12)
@@ -36,14 +36,7 @@
static void set_pch_cpu_strap(u8 flex_ratio)
{
- uint8_t *spibar = (void *)SPI_BASE_ADDRESS;
- u32 ssl, ssms, soft_reset_data;
-
-
- /* Set Strap Lock Disable */
- ssl = read32(spibar + SPIBAR_RESET_LOCK);
- ssl |= SPIBAR_RESET_LOCK_DISABLE;
- write32(spibar + SPIBAR_RESET_LOCK, ssl);
+ u32 soft_reset_data;
/* Soft Reset Data Register Bit 12 = MAX Boot Frequency
* Bit 6-11 = Flex Ratio
@@ -51,17 +44,7 @@ static void set_pch_cpu_strap(u8 flex_ratio)
*/
soft_reset_data = SPI_STRAP_MAX_FREQ;
soft_reset_data |= (flex_ratio << FLEX_RATIO_BIT);
- write32(spibar + SPIBAR_RESET_DATA, soft_reset_data);
-
- /* Set Strap Mux Select set to '1' */
- ssms = read32(spibar + SPIBAR_RESET_CTRL);
- ssms |= SPIBAR_RESET_CTRL_SSMC;
- write32(spibar + SPIBAR_RESET_CTRL, ssms);
-
- /* Set Strap Lock Enable */
- ssl = read32(spibar + SPIBAR_RESET_LOCK);
- ssl |= SPIBAR_RESET_LOCK_ENABLE;
- write32(spibar + SPIBAR_RESET_LOCK, ssl);
+ fast_spi_set_strap_msg_data(soft_reset_data);
}
static void set_flex_ratio_to_tdp_nominal(void)
diff --git a/src/soc/intel/skylake/bootblock/pch.c b/src/soc/intel/skylake/bootblock/pch.c
index 01bff0bf33..a92e4cffba 100644
--- a/src/soc/intel/skylake/bootblock/pch.c
+++ b/src/soc/intel/skylake/bootblock/pch.c
@@ -18,6 +18,7 @@
#include <chip.h>
#include <device/device.h>
#include <device/pci_def.h>
+#include <intelblocks/fast_spi.h>
#include <intelblocks/itss.h>
#include <intelblocks/pcr.h>
#include <intelblocks/rtc.h>
@@ -46,38 +47,6 @@
#define PCR_DMI_LPCIOD 0x2770
#define PCR_DMI_LPCIOE 0x2774
-/*
- * Enable Prefetching and Caching.
- */
-static void enable_spi_prefetch(void)
-{
- u8 reg8 = pci_read_config8(PCH_DEV_SPI, 0xdc);
- reg8 &= ~(3 << 2);
- reg8 |= (2 << 2); /* Prefetching and Caching Enabled */
- pci_write_config8(PCH_DEV_SPI, 0xdc, reg8);
-}
-
-static void enable_spibar(void)
-{
- device_t dev = PCH_DEV_SPI;
- u8 pcireg;
-
- /* Assign Resources to SPI Controller */
- /* Clear BIT 1-2 SPI Command Register */
- pcireg = pci_read_config8(dev, PCI_COMMAND);
- pcireg &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
- pci_write_config8(dev, PCI_COMMAND, pcireg);
-
- /* Program Temporary BAR for SPI */
- pci_write_config32(dev, PCI_BASE_ADDRESS_0,
- SPI_BASE_ADDRESS | PCI_BASE_ADDRESS_SPACE_MEMORY);
-
- /* Enable Bus Master and MMIO Space */
- pcireg = pci_read_config8(dev, PCI_COMMAND);
- pcireg |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
- pci_write_config8(dev, PCI_COMMAND, pcireg);
-}
-
static void enable_p2sbbar(void)
{
device_t dev = PCH_DEV_P2SB;
@@ -99,8 +68,7 @@ static void enable_p2sbbar(void)
void bootblock_pch_early_init(void)
{
- enable_spibar();
- enable_spi_prefetch();
+ fast_spi_early_init(SPI_BASE_ADDRESS);
enable_p2sbbar();
}