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author | Alexandru Gagniuc <mr.nuke.me@gmail.com> | 2015-09-30 20:23:09 -0700 |
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committer | Alexandru Gagniuc <mr.nuke.me@gmail.com> | 2015-10-15 03:52:49 +0000 |
commit | 86091f94b6ca58f4b8795503b274492d6a935c15 (patch) | |
tree | db6e5f77dc57850b25574aed5063743ca4bc4d48 /src/soc/intel/skylake/bootblock | |
parent | 58562405c8c416a415652516b8af31b204b4ff0d (diff) | |
download | coreboot-86091f94b6ca58f4b8795503b274492d6a935c15.tar.xz |
cpu/mtrr.h: Fix macro names for MTRR registers
We use UNDERSCORE_CASE. For the MTRR macros that refer to an MSR,
we also remove the _MSR suffix, as they are, by definition, MSRs.
Change-Id: Id4483a75d62cf1b478a9105ee98a8f55140ce0ef
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/11761
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/soc/intel/skylake/bootblock')
-rw-r--r-- | src/soc/intel/skylake/bootblock/cpu.c | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/src/soc/intel/skylake/bootblock/cpu.c b/src/soc/intel/skylake/bootblock/cpu.c index 3a29972370..70bf928761 100644 --- a/src/soc/intel/skylake/bootblock/cpu.c +++ b/src/soc/intel/skylake/bootblock/cpu.c @@ -45,10 +45,10 @@ static void set_var_mtrr( msr_t basem, maskm; basem.lo = base | type; basem.hi = 0; - wrmsr(MTRRphysBase_MSR(reg), basem); - maskm.lo = ~(size - 1) | MTRRphysMaskValid; + wrmsr(MTRR_PHYS_BASE(reg), basem); + maskm.lo = ~(size - 1) | MTRR_PHYS_MASK_VALID; maskm.hi = (1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1; - wrmsr(MTRRphysMask_MSR(reg), maskm); + wrmsr(MTRR_PHYS_MASK(reg), maskm); } static void enable_rom_caching(void) @@ -62,7 +62,7 @@ static void enable_rom_caching(void) /* Enable Variable MTRRs */ msr.hi = 0x00000000; msr.lo = 0x00000800; - wrmsr(MTRRdefType_MSR, msr); + wrmsr(MTRR_DEF_TYPE_MSR, msr); } static void bootblock_mdelay(int ms) @@ -164,14 +164,14 @@ static void set_flex_ratio_to_tdp_nominal(void) static void check_for_clean_reset(void) { msr_t msr; - msr = rdmsr(MTRRdefType_MSR); + msr = rdmsr(MTRR_DEF_TYPE_MSR); /* * Use the MTRR default type MSR as a proxy for detecting INIT#. * Reset the system if any known bits are set in that MSR. That is * an indication of the CPU not being properly reset. */ - if (msr.lo & (MTRRdefTypeEn | MTRRdefTypeFixEn)) + if (msr.lo & (MTRR_DEF_TYPE_EN | MTRR_DEF_TYPE_FIX_EN)) soft_reset(); } @@ -191,7 +191,7 @@ static void patch_microcode(void) * MTRRCAP[12]. Check for this feature and avoid reloading the * same microcode during early cpu initialization. */ - msr = rdmsr(MTRRcap_MSR); + msr = rdmsr(MTRR_CAP_MSR); if ((msr.lo & PRMRR_SUPPORTED) && (current_rev != patch->rev - 1)) intel_update_microcode_from_cbfs(); } |