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authorSubrata Banik <subrata.banik@intel.com>2017-03-14 18:24:47 +0530
committerMartin Roth <martinroth@google.com>2017-03-28 16:40:13 +0200
commit93ebe499d45679a250de780d8a8b73d32d7ea00e (patch)
treec40c6bd71a771df26f94d028718f15ec89444afd /src/soc/intel/skylake/bootblock
parent01ae11b057e4b15e1fde48c7845f7fbf66a4e948 (diff)
downloadcoreboot-93ebe499d45679a250de780d8a8b73d32d7ea00e.tar.xz
soc/intel/skylake: Clean up code by using common System Agent module
This patch currently contains the SA initialization required for bootblock phase - 1. Use SOC_INTEL_COMMON_BLOCK_SA kconfig for common SA code. 2. Perform PCIEXBAR programming based on soc configurable PCIEX_LENGTH_xxxMB 3. Use common systemagent header file. Change-Id: I0fa0a60f680b9b00b7f26f1875c553612b123a8e Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/18566 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/soc/intel/skylake/bootblock')
-rw-r--r--src/soc/intel/skylake/bootblock/systemagent.c43
1 files changed, 0 insertions, 43 deletions
diff --git a/src/soc/intel/skylake/bootblock/systemagent.c b/src/soc/intel/skylake/bootblock/systemagent.c
deleted file mode 100644
index e76d4d25e9..0000000000
--- a/src/soc/intel/skylake/bootblock/systemagent.c
+++ /dev/null
@@ -1,43 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Google Inc.
- * Copyright (C) 2015 Intel Corporation.
- * Copyright (C) 2016 Intel Corporation.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/io.h>
-#include <soc/bootblock.h>
-#include <soc/pci_devs.h>
-#include <soc/systemagent.h>
-
-void bootblock_systemagent_early_init(void)
-{
- uint32_t reg;
-
- /*
- * The "io" variant of the config access is explicitly used to
- * setup the PCIEXBAR because CONFIG_MMCONF_SUPPORT is set to
- * to true. That way all subsequent non-explicit config accesses use
- * MCFG. This code also assumes that bootblock_northbridge_init() is
- * the first thing called in the non-asm boot block code. The final
- * assumption is that no assembly code is using the
- * CONFIG_MMCONF_SUPPORT option to do PCI config acceses.
- *
- * The PCIEXBAR is assumed to live in the memory mapped IO space under
- * 4GiB.
- */
- reg = 0;
- pci_io_write_config32(SA_DEV_ROOT, PCIEXBAR + 4, reg);
- reg = CONFIG_MMCONF_BASE_ADDRESS | 4 | 1; /* 64MiB - 0-63 buses. */
- pci_io_write_config32(SA_DEV_ROOT, PCIEXBAR, reg);
-}