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authorSubrata Banik <subrata.banik@intel.com>2017-03-03 18:06:06 +0530
committerAaron Durbin <adurbin@chromium.org>2017-03-06 20:45:40 +0100
commitda1d802ec447cf61c568698632aff3578ac5531a (patch)
tree35ab95c734c4d35e14b870603d5332e878219007 /src/soc/intel/skylake/bootblock
parente074d62e181c58d0cd215f93af7c8e70e2e31601 (diff)
downloadcoreboot-da1d802ec447cf61c568698632aff3578ac5531a.tar.xz
soc/intel/skylake: Clean up CPU code
Use header (soc/intel/common/block/include/intelblocks/msr.h) for MSR macros Change-Id: I401b92cda54b6140f2fe23a6447dad89879a5ef0 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/18554 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/skylake/bootblock')
-rw-r--r--src/soc/intel/skylake/bootblock/cpu.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/intel/skylake/bootblock/cpu.c b/src/soc/intel/skylake/bootblock/cpu.c
index 3cea8bdcfc..c6ede53937 100644
--- a/src/soc/intel/skylake/bootblock/cpu.c
+++ b/src/soc/intel/skylake/bootblock/cpu.c
@@ -126,7 +126,7 @@ void set_max_freq(void)
}
perf_ctl.hi = 0;
- wrmsr(IA32_PERF_CTL, perf_ctl);
+ wrmsr(MSR_IA32_PERF_CTL, perf_ctl);
printk(BIOS_DEBUG, "CPU: frequency set to %d MHz\n",
((perf_ctl.lo >> 8) & 0xff) * CPU_BCLK);