diff options
| author | Michael Niewöhner <foss@mniewoehner.de> | 2019-10-05 19:47:47 +0200 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2019-10-26 15:39:40 +0000 |
| commit | 0f91f79447b63b846fe0da770404bf18833f1306 (patch) | |
| tree | bfce597f2a795a1194803afec57666e17dba3508 /src/soc/intel/skylake/bootblock | |
| parent | a9e07f94448650b3a9a27062775c642f8939464b (diff) | |
| download | coreboot-0f91f79447b63b846fe0da770404bf18833f1306.tar.xz | |
soc/intel/skylake: drop support for FSP 1.1
This drops support for FSP 1.1 in soc/intel/skylake, after all boards
have been migrated to FSP 2.0, which is backwards compatible.
Any moving of files happens in a follow-up commit to make review easier.
Change-Id: I0dd2eab0edfda0545ff94c3908b8574d5ad830bd
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35813
Reviewed-by: Michael Niewöhner
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/skylake/bootblock')
| -rw-r--r-- | src/soc/intel/skylake/bootblock/bootblock.c | 4 |
1 files changed, 0 insertions, 4 deletions
diff --git a/src/soc/intel/skylake/bootblock/bootblock.c b/src/soc/intel/skylake/bootblock/bootblock.c index e9ca2d8af2..596e3f184f 100644 --- a/src/soc/intel/skylake/bootblock/bootblock.c +++ b/src/soc/intel/skylake/bootblock/bootblock.c @@ -38,10 +38,6 @@ void bootblock_soc_early_init(void) void bootblock_soc_init(void) { - /* FSP 2.0 does not provide FSP-T/TempRamInit init support yet */ - if (CONFIG(PLATFORM_USES_FSP1_1)) - bootblock_fsp_temp_ram_init(); - /* * Perform early chipset initialization before fsp memory init * example: pirq->irq programming, enabling smbus, set pmcbase |