diff options
| author | Usha P <usha.p@intel.com> | 2019-11-08 16:00:40 +0530 |
|---|---|---|
| committer | Subrata Banik <subrata.banik@intel.com> | 2019-11-22 06:26:27 +0000 |
| commit | 56715ec23f6c34ae4bda3ac197aba0d90af06660 (patch) | |
| tree | 5fe15ad1ebd88a9389dc0d5f8b3f39c754d4d92c /src/soc/intel/skylake/bootblock | |
| parent | f8dc4bc0224f18a33fcf19e3d754ac96a383a863 (diff) | |
| download | coreboot-56715ec23f6c34ae4bda3ac197aba0d90af06660.tar.xz | |
soc/intel/skylake: Refactor pch_early_init() code
This patch keeps required pch_early_init() function like ABASE programming,
GPE and RTC init into bootblock and moves remaining functions like
TCO configuration and SMBUS init into romstage/pch.c in order to maintain
only required chipset programming for bootblock and verstage.
TEST=Able to build and boot soraka.
Change-Id: Idf7b04edc3fce147f7857591ce7d5a0cd03f43fe
Signed-off-by: Usha P <usha.p@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36672
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Diffstat (limited to 'src/soc/intel/skylake/bootblock')
| -rw-r--r-- | src/soc/intel/skylake/bootblock/bootblock.c | 3 | ||||
| -rw-r--r-- | src/soc/intel/skylake/bootblock/pch.c | 14 |
2 files changed, 3 insertions, 14 deletions
diff --git a/src/soc/intel/skylake/bootblock/bootblock.c b/src/soc/intel/skylake/bootblock/bootblock.c index 596e3f184f..d1fbb83b8a 100644 --- a/src/soc/intel/skylake/bootblock/bootblock.c +++ b/src/soc/intel/skylake/bootblock/bootblock.c @@ -44,7 +44,6 @@ void bootblock_soc_init(void) * and abase, i2c programming and print platform info */ report_platform_info(); - pch_early_init(); - + pch_init(); gspi_early_bar_init(); } diff --git a/src/soc/intel/skylake/bootblock/pch.c b/src/soc/intel/skylake/bootblock/pch.c index c95a8d80e8..332060ed2d 100644 --- a/src/soc/intel/skylake/bootblock/pch.c +++ b/src/soc/intel/skylake/bootblock/pch.c @@ -2,7 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015-2018 Intel Corporation. + * Copyright (C) 2015-2019 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -24,8 +24,6 @@ #include <intelblocks/pcr.h> #include <intelblocks/pmclib.h> #include <intelblocks/rtc.h> -#include <intelblocks/smbus.h> -#include <intelblocks/tco.h> #include <soc/bootblock.h> #include <soc/iomap.h> #include <soc/p2sb.h> @@ -34,8 +32,6 @@ #include <soc/pcr_ids.h> #include <soc/pm.h> #include <soc/pmc.h> -#include <soc/smbus.h> - #include "../chip.h" #define PCR_DMI_DMICTL 0x2234 @@ -150,7 +146,7 @@ void pch_early_iorange_init(void) pch_enable_lpc(); } -void pch_early_init(void) +void pch_init(void) { /* * Enabling ABASE for accessing PM1_STS, PM1_EN, PM1_CNT, @@ -164,12 +160,6 @@ void pch_early_init(void) */ soc_config_pwrmbase(); - /* Programming TCO_BASE_ADDRESS and TCO Timer Halt */ - tco_configure(); - - /* Program SMBUS_BASE_ADDRESS and Enable it */ - smbus_common_init(); - /* Set up GPE configuration */ pmc_gpe_init(); |