soc/intel/skylake: Add C entry bootblock support

List of activity performing in this patch
- early PCH programming
- early SA programming
- early CPU programming
- mainborad early gpio programming for UART and SPI
- car setup
- move chipset programming from verstage to post console

BUG=chrome-os-partner:55357
BRANCH=none
TEST=Built and booted kunimitsu till POST code 0x34

Change-Id: If20ab869de62cd4439f3f014f9362ccbec38e143
Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Signed-off-by: Naveen Krishna Chatradhi <naveenkrishna.ch@intel.com>
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/15785
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

5 files changed, 121 insertions, 65 deletions

diff --git a/src/soc/intel/skylake/bootblock/bootblock.c b/src/soc/intel/skylake/bootblock/bootblock.c
index c7ec937566..028bb7b314 100644
--- a/src/soc/intel/skylake/bootblock/bootblock.c
+++ b/src/soc/intel/skylake/bootblock/bootblock.c
@@ -14,9 +14,34 @@
  */
 
 #include <bootblock_common.h>
+#include <soc/bootblock.h>
+#include <soc/romstage.h>
 
 void asmlinkage bootblock_c_entry(uint64_t base_timestamp)
 {
 	/* Call lib/bootblock.c main */
 	bootblock_main_with_timestamp(base_timestamp);
-}
\ No newline at end of file
+}
+
+void bootblock_soc_early_init(void)
+{
+	bootblock_systemagent_early_init();
+	bootblock_pch_early_init();
+	bootblock_cpu_init();
+
+	if (IS_ENABLED(CONFIG_BOOTBLOCK_CONSOLE))
+		pch_uart_init();
+}
+
+/*
+ * Perform early chipset initialization before fsp memory init
+ * example: pirq->irq programming, enabling smbus, pmcbase, abase,
+ * 			get platform info, i2c programming
+ */
+void bootblock_soc_init(void)
+{
+	report_platform_info();
+	set_max_freq();
+	pch_early_init();
+	i2c_early_init();
+}
diff --git a/src/soc/intel/skylake/bootblock/cpu.c b/src/soc/intel/skylake/bootblock/cpu.c
index d713974358..8c1e58a65f 100644
--- a/src/soc/intel/skylake/bootblock/cpu.c
+++ b/src/soc/intel/skylake/bootblock/cpu.c
@@ -15,14 +15,11 @@
  */
 
 #include <stdint.h>
-#include <arch/cpu.h>
-#include <cpu/x86/cache.h>
-#include <cpu/x86/msr.h>
-#include <cpu/x86/mtrr.h>
-#include <device/pci_def.h>
+#include <delay.h>
 #include <arch/io.h>
 #include <cpu/intel/microcode/microcode.c>
 #include <reset.h>
+#include <soc/bootblock.h>
 #include <soc/iomap.h>
 #include <soc/msr.h>
 #include <soc/pci_devs.h>
@@ -33,45 +30,6 @@
 /* Soft Reset Data Register Bit 6-11 = Flex Ratio */
 #define FLEX_RATIO_BIT	6
 
-static void set_var_mtrr(
-	unsigned reg, unsigned base, unsigned size, unsigned type)
-
-{
-	/* Bit Bit 32-35 of MTRRphysMask should be set to 1 */
-	msr_t basem, maskm;
-	basem.lo = base | type;
-	basem.hi = 0;
-	wrmsr(MTRR_PHYS_BASE(reg), basem);
-	maskm.lo = ~(size - 1) | MTRR_PHYS_MASK_VALID;
-	maskm.hi = (1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1;
-	wrmsr(MTRR_PHYS_MASK(reg), maskm);
-}
-
-static void enable_rom_caching(void)
-{
-	msr_t msr;
-
-	disable_cache();
-	set_var_mtrr(1, CACHE_ROM_BASE, CACHE_ROM_SIZE, MTRR_TYPE_WRPROT);
-	enable_cache();
-
-	/* Enable Variable MTRRs */
-	msr.hi = 0x00000000;
-	msr.lo = 0x00000800;
-	wrmsr(MTRR_DEF_TYPE_MSR, msr);
-}
-
-static void bootblock_mdelay(int ms)
-{
-	u32 target = ms * 24 * 1000;
-	msr_t current;
-	msr_t start = rdmsr(MSR_COUNTER_24_MHZ);
-
-	do {
-		current = rdmsr(MSR_COUNTER_24_MHZ);
-	} while ((current.lo - start.lo) < target);
-}
-
 static void set_pch_cpu_strap(u8 flex_ratio)
 {
 	uint8_t *spibar = (void *)SPI_BASE_ADDRESS;
@@ -135,31 +93,15 @@ static void set_flex_ratio_to_tdp_nominal(void)
 	set_pch_cpu_strap(nominal_ratio);
 
 	/* Delay before reset to avoid potential TPM lockout */
-	bootblock_mdelay(30);
+	mdelay(30);
 
 	/* Issue soft reset, will be "CPU only" due to soft reset data */
 	soft_reset();
 }
 
-static void check_for_clean_reset(void)
-{
-	msr_t msr;
-	msr = rdmsr(MTRR_DEF_TYPE_MSR);
-
-	/*
-	 * Use the MTRR default type MSR as a proxy for detecting INIT#.
-	 * Reset the system if any known bits are set in that MSR. That is
-	 * an indication of the CPU not being properly reset.
-	 */
-	if (msr.lo & (MTRR_DEF_TYPE_EN | MTRR_DEF_TYPE_FIX_EN))
-		soft_reset();
-}
-
-static void bootblock_cpu_init(void)
+void bootblock_cpu_init(void)
 {
 	/* Set flex ratio and reset if needed */
 	set_flex_ratio_to_tdp_nominal();
-	check_for_clean_reset();
-	enable_rom_caching();
 	intel_update_microcode_from_cbfs();
 }
diff --git a/src/soc/intel/skylake/bootblock/pch.c b/src/soc/intel/skylake/bootblock/pch.c
index 94ed844d3b..569611502e 100644
--- a/src/soc/intel/skylake/bootblock/pch.c
+++ b/src/soc/intel/skylake/bootblock/pch.c
@@ -3,6 +3,7 @@
  *
  * Copyright (C) 2014 Google Inc.
  * Copyright (C) 2015 Intel Corporation.
+ * Copyright (C) 2016 Intel Corporation.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -14,9 +15,11 @@
  * GNU General Public License for more details.
  */
 #include <arch/io.h>
+#include <soc/bootblock.h>
 #include <soc/iomap.h>
 #include <soc/lpc.h>
 #include <soc/pci_devs.h>
+#include <soc/pcr.h>
 #include <soc/spi.h>
 
 /*
@@ -51,8 +54,21 @@ static void enable_spibar(void)
 	pci_write_config8(dev, PCI_COMMAND, pcireg);
 }
 
-static void bootblock_southbridge_init(void)
+static void enable_p2sbbar(void)
+{
+	device_t dev = PCH_DEV_P2SB;
+
+	/* Enable PCR Base address in PCH */
+	pci_write_config32(dev, PCI_BASE_ADDRESS_0, PCH_PCR_BASE_ADDRESS);
+
+	/* Enable P2SB MSE */
+	pci_write_config8(dev, PCI_COMMAND,
+			  PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
+}
+
+void bootblock_pch_early_init(void)
 {
 	enable_spibar();
 	enable_spi_prefetch();
+	enable_p2sbbar();
 }
diff --git a/src/soc/intel/skylake/bootblock/systemagent.c b/src/soc/intel/skylake/bootblock/systemagent.c
index a65be99429..608110e253 100644
--- a/src/soc/intel/skylake/bootblock/systemagent.c
+++ b/src/soc/intel/skylake/bootblock/systemagent.c
@@ -3,6 +3,7 @@
  *
  * Copyright (C) 2014 Google Inc.
  * Copyright (C) 2015 Intel Corporation.
+ * Copyright (C) 2016 Intel Corporation.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -15,10 +16,11 @@
  */
 
 #include <arch/io.h>
+#include <soc/bootblock.h>
 #include <soc/pci_devs.h>
 #include <soc/systemagent.h>
 
-static void bootblock_northbridge_init(void)
+void bootblock_systemagent_early_init(void)
 {
 	uint32_t reg;
 
diff --git a/src/soc/intel/skylake/bootblock/uart.c b/src/soc/intel/skylake/bootblock/uart.c
new file mode 100644
index 0000000000..ff1687c520
--- /dev/null
+++ b/src/soc/intel/skylake/bootblock/uart.c
@@ -0,0 +1,71 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Google Inc.
+ * Copyright (C) 2015 Intel Corporation
+ * Copyright (C) 2016 Intel Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/io.h>
+#include <console/uart.h>
+#include <device/pci_def.h>
+#include <stdint.h>
+#include <soc/bootblock.h>
+#include <soc/pci_devs.h>
+#include <soc/pcr.h>
+#include <soc/serialio.h>
+#include <gpio.h>
+
+/* UART2 pad configuration. Support RXD and TXD for now. */
+static const struct pad_config uart2_pads[] = {
+/* UART2_RXD */		PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),
+/* UART2_TXD */		PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),
+};
+
+void pch_uart_init(void)
+{
+	device_t dev = PCH_DEV_UART2;
+	u32 tmp;
+	u8 *base = (void *)uart_platform_base(CONFIG_UART_FOR_CONSOLE);
+
+	/* Set configured UART2 base address */
+	pci_write_config32(dev, PCI_BASE_ADDRESS_0, (u32)base);
+
+	/* Enable memory access and bus master */
+	tmp = pci_read_config32(dev, PCI_COMMAND);
+	tmp |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
+	pci_write_config32(dev, PCI_COMMAND, tmp);
+
+	/* Take UART2 out of reset */
+	tmp = read32(base + SIO_REG_PPR_RESETS);
+	tmp |= SIO_REG_PPR_RESETS_FUNC | SIO_REG_PPR_RESETS_APB |
+		SIO_REG_PPR_RESETS_IDMA;
+	write32(base + SIO_REG_PPR_RESETS, tmp);
+
+	/*
+	 * Set M and N divisor inputs and enable clock.
+	 * Main reference frequency to UART is:
+	 * 120MHz * M / N = 120MHz * 48 / 3125 = 1843200Hz
+	 */
+	tmp = read32(base + SIO_REG_PPR_CLOCK);
+	tmp |= SIO_REG_PPR_CLOCK_EN | SIO_REG_PPR_CLOCK_UPDATE |
+		(SIO_REG_PPR_CLOCK_N_DIV << 16) |
+		(SIO_REG_PPR_CLOCK_M_DIV << 1);
+	write32(base + SIO_REG_PPR_CLOCK, tmp);
+
+	/* Put UART2 in byte access mode for 16550 compatibility */
+	if (!IS_ENABLED(CONFIG_DRIVERS_UART_8250MEM_32))
+		pcr_andthenor32(PID_SERIALIO,
+		R_PCH_PCR_SERIAL_IO_GPPRVRW7, 0, SIO_PCH_LEGACY_UART2);
+
+	gpio_configure_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
+}