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authorJulius Werner <jwerner@chromium.org>2019-03-05 16:53:33 -0800
committerPatrick Georgi <pgeorgi@google.com>2019-03-08 08:33:24 +0000
commitcd49cce7b70e80b4acc49b56bb2bb94370b4d867 (patch)
tree8e89136e2da7cf54453ba8c112eda94415b56242 /src/soc/intel/skylake/bootblock
parentb3a8cc54dbaf833c590a56f912209a5632b71f49 (diff)
downloadcoreboot-cd49cce7b70e80b4acc49b56bb2bb94370b4d867.tar.xz
coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)
This patch is a raw application of find src/ -type f | xargs sed -i -e 's/IS_ENABLED\s*(CONFIG_/CONFIG(/g' Change-Id: I6262d6d5c23cabe23c242b4f38d446b74fe16b88 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31774 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/soc/intel/skylake/bootblock')
-rw-r--r--src/soc/intel/skylake/bootblock/bootblock.c4
-rw-r--r--src/soc/intel/skylake/bootblock/pch.c6
2 files changed, 5 insertions, 5 deletions
diff --git a/src/soc/intel/skylake/bootblock/bootblock.c b/src/soc/intel/skylake/bootblock/bootblock.c
index acf25ffd48..4358fba40f 100644
--- a/src/soc/intel/skylake/bootblock/bootblock.c
+++ b/src/soc/intel/skylake/bootblock/bootblock.c
@@ -32,14 +32,14 @@ void bootblock_soc_early_init(void)
bootblock_cpu_init();
pch_early_iorange_init();
- if (IS_ENABLED(CONFIG_INTEL_LPSS_UART_FOR_CONSOLE))
+ if (CONFIG(INTEL_LPSS_UART_FOR_CONSOLE))
uart_bootblock_init();
}
void bootblock_soc_init(void)
{
/* FSP 2.0 does not provide FSP-T/TempRamInit init support yet */
- if (IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1))
+ if (CONFIG(PLATFORM_USES_FSP1_1))
bootblock_fsp_temp_ram_init();
/*
diff --git a/src/soc/intel/skylake/bootblock/pch.c b/src/soc/intel/skylake/bootblock/pch.c
index 34cc713124..0f6c8a85d4 100644
--- a/src/soc/intel/skylake/bootblock/pch.c
+++ b/src/soc/intel/skylake/bootblock/pch.c
@@ -71,7 +71,7 @@ static void soc_config_acpibase(void)
*/
reg32 = ((0x3f << 18) | ACPI_BASE_ADDRESS | 1);
pcr_write32(PID_DMI, PCR_DMI_ACPIBA, reg32);
- if (IS_ENABLED(CONFIG_SKYLAKE_SOC_PCH_H))
+ if (CONFIG(SKYLAKE_SOC_PCH_H))
pcr_write32(PID_DMI, PCR_DMI_ACPIBDID, 0x23a8);
else
pcr_write32(PID_DMI, PCR_DMI_ACPIBDID, 0x23a0);
@@ -105,7 +105,7 @@ static void soc_config_pwrmbase(void)
pcr_write32(PID_DMI, PCR_DMI_PMBASEA,
((PCH_PWRM_BASE_ADDRESS & 0xFFFF0000) |
(PCH_PWRM_BASE_ADDRESS >> 16)));
- if (IS_ENABLED(CONFIG_SKYLAKE_SOC_PCH_H))
+ if (CONFIG(SKYLAKE_SOC_PCH_H))
pcr_write32(PID_DMI, PCR_DMI_PMBASEC, 0x800023a8);
else
pcr_write32(PID_DMI, PCR_DMI_PMBASEC, 0x800023a0);
@@ -131,7 +131,7 @@ void pch_early_iorange_init(void)
LPC_IOE_EC_62_66;
/* IO Decode Range */
- if (IS_ENABLED(CONFIG_DRIVERS_UART_8250IO))
+ if (CONFIG(DRIVERS_UART_8250IO))
lpc_io_setup_comm_a_b();
/* IO Decode Enable */