diff options
| author | Subrata Banik <subrata.banik@intel.com> | 2016-11-22 20:21:49 +0530 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-11-28 19:00:36 +0100 |
| commit | 2c3054c14eed154abf10a504c05919aaf4db496e (patch) | |
| tree | 25e60699534162b0cbcb6c3b6ddb845bb997e0bb /src/soc/intel/skylake/chip.c | |
| parent | 2c6a8060da994bb22eb1619d55ee74be096682b5 (diff) | |
| download | coreboot-2c3054c14eed154abf10a504c05919aaf4db496e.tar.xz | |
soc/intel/skylake: Add USB Port Over Current (OC) Pin programming
Program USB Overcurrent pins as per board schematics definition.
BUG=none
BRANCH=none
TEST=Build and boot kunimitsu from USB device.
Change-Id: I6aeb65953c753e09ad639469de7d866a54f42f11
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/17570
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Diffstat (limited to 'src/soc/intel/skylake/chip.c')
| -rw-r--r-- | src/soc/intel/skylake/chip.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c index 2703224883..c64a8df589 100644 --- a/src/soc/intel/skylake/chip.c +++ b/src/soc/intel/skylake/chip.c @@ -90,6 +90,8 @@ void soc_silicon_init_params(SILICON_INIT_UPD *params) for (i = 0; i < ARRAY_SIZE(config->usb2_ports); i++) { params->PortUsb20Enable[i] = config->usb2_ports[i].enable; + params->Usb2OverCurrentPin[i] = + config->usb2_ports[i].ocpin; params->Usb2AfePetxiset[i] = config->usb2_ports[i].pre_emp_bias; params->Usb2AfeTxiset[i] = @@ -102,6 +104,7 @@ void soc_silicon_init_params(SILICON_INIT_UPD *params) for (i = 0; i < ARRAY_SIZE(config->usb3_ports); i++) { params->PortUsb30Enable[i] = config->usb3_ports[i].enable; + params->Usb3OverCurrentPin[i] = config->usb3_ports[i].ocpin; if (config->usb3_ports[i].tx_de_emp) { params->Usb3HsioTxDeEmphEnable[i] = 1; params->Usb3HsioTxDeEmph[i] = |