diff options
author | Martin Roth <martinroth@google.com> | 2017-06-03 20:03:18 -0600 |
---|---|---|
committer | Patrick Georgi <pgeorgi@google.com> | 2017-06-07 12:09:15 +0200 |
commit | e18e6427d0f3261f9ec361d4418b8fe1dd7cc469 (patch) | |
tree | f6a10fc93dddada7e49108a5ad06e71590f2d54c /src/soc/intel/skylake/chip.c | |
parent | e81ce0483db982c741eebdda649111eee22a853b (diff) | |
download | coreboot-e18e6427d0f3261f9ec361d4418b8fe1dd7cc469.tar.xz |
src: change coreboot to lowercase
The word 'coreboot' should always be written in lowercase, even at the
start of a sentence.
Change-Id: I7945ddb988262e7483da4e623cedf972380e65a2
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20029
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/soc/intel/skylake/chip.c')
-rw-r--r-- | src/soc/intel/skylake/chip.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c index 61975c648c..ab069488a0 100644 --- a/src/soc/intel/skylake/chip.c +++ b/src/soc/intel/skylake/chip.c @@ -182,7 +182,7 @@ void soc_silicon_init_params(SILICON_INIT_UPD *params) * To disable Heci, the Psf needs to be left unlocked * by FSP after end of post sequence. Based on the devicetree * setting, we set the appropriate PsfUnlock policy in Fsp, - * do the changes and then lock it back in Coreboot + * do the changes and then lock it back in coreboot * */ if (config->HeciEnabled == 0) |