diff options
| author | Lee Leahy <leroy.p.leahy@intel.com> | 2017-03-16 16:44:36 -0700 |
|---|---|---|
| committer | Lee Leahy <leroy.p.leahy@intel.com> | 2017-03-17 02:34:52 +0100 |
| commit | b439a929392ba54dee43455f6e164b884cb8c308 (patch) | |
| tree | ffc44834d8ff6144d360a356dab0688e006945af /src/soc/intel/skylake/chip.h | |
| parent | 573564cca8cd01cadf179546b8b124694fd3dcbb (diff) | |
| download | coreboot-b439a929392ba54dee43455f6e164b884cb8c308.tar.xz | |
soc/intel/skylake: Wrap lines at 80 columns
Fix the following warning detected by checkpatch:
WARNING: line over 80 characters
TEST=Build for glados
Change-Id: I79341f46ca06ac052f987975ccaf975470d27806
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18867
Tested-by: build bot (Jenkins)
Reviewed-by: Lee Leahy <leroy.p.leahy@intel.com>
Diffstat (limited to 'src/soc/intel/skylake/chip.h')
| -rw-r--r-- | src/soc/intel/skylake/chip.h | 14 |
1 files changed, 9 insertions, 5 deletions
diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index 17b34b72e8..4aa7ec9f78 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -265,9 +265,10 @@ struct soc_intel_skylake_config { u8 LockDownConfigBiosLock; /* * Enable InSMM.STS (EISS) in SPI If this bit is set, then WPD must be a - * '1' and InSMM.STS must be '1' also in order to write to BIOS regions of - * SPI Flash. If this bit is clear, then the InSMM.STS is a don't care. The - * BIOS must set the EISS bit while BIOS Guard support is enabled. + * '1' and InSMM.STS must be '1' also in order to write to BIOS regions + * of SPI Flash. If this bit is clear, then the InSMM.STS is a don't + * care. The BIOS must set the EISS bit while BIOS Guard support is + * enabled. */ u8 LockDownConfigSpiEiss; /* Subsystem Vendor ID of the PCH devices*/ @@ -325,7 +326,8 @@ struct soc_intel_skylake_config { */ u8 PmConfigPciClockRun; /* - * SLP_X Stretching After SUS Well Power Up. Values 0: Disabled, 1: Enabled + * SLP_X Stretching After SUS Well Power Up. Values 0: Disabled, + * 1: Enabled */ u8 PmConfigSlpStrchSusUp; /* @@ -349,7 +351,9 @@ struct soc_intel_skylake_config { u8 PmConfigPwrCycDur; /* Determines if enable Serial IRQ. Values 0: Disabled, 1: Enabled.*/ u8 SerialIrqConfigSirqEnable; - /* Serial IRQ Mode Select. Values: 0: PchQuietMode, 1: PchContinuousMode.*/ + /* Serial IRQ Mode Select. Values: 0: PchQuietMode, + * 1: PchContinuousMode. + */ u8 SerialIrqConfigSirqMode; /* * Start Frame Pulse Width. |