summaryrefslogtreecommitdiff
path: root/src/soc/intel/skylake/chip.h
diff options
context:
space:
mode:
authorGaggery Tsai <gaggery.tsai@intel.com>2018-01-15 15:03:01 +0800
committerShelley Chen <shchen@google.com>2018-02-06 06:14:30 +0000
commitda6f4ae0b98313aae9e6295e412d87b11199501f (patch)
tree1add48cfd2fbb497301c0f1a3f07d495c43849ca /src/soc/intel/skylake/chip.h
parentc12dff9098fb4023b878102fd5eecdb10c37fcdb (diff)
downloadcoreboot-da6f4ae0b98313aae9e6295e412d87b11199501f.tar.xz
soc/intel/skylake: Set PsysPmax value
According to doc #543977 Power Architecture Guide, PsysPmax is the maximum platform power. It maps to the full-scale of Psys signal. This patch adds a "psys_pmax" member in chip information which allows boards to set up maximum platform power. BUG=b:71594855 BRANCH=None TEST=Set "psys_pmax" in device tree & "USE=fw_debug emerge-fizz chromeos-mrc coreboot chromeos-bootimage" & ensure correct PsysPmax value is passed to FSP-S through UPD. Verfied on KBL-R and KBL-U SKUs. Change-Id: I44f2e2917a8eb9ce3bb69d9c15899d4c7c5b2883 Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com> Reviewed-on: https://review.coreboot.org/23268 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc/intel/skylake/chip.h')
-rw-r--r--src/soc/intel/skylake/chip.h3
1 files changed, 3 insertions, 0 deletions
diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h
index 7c95ec1b0e..003c44fc91 100644
--- a/src/soc/intel/skylake/chip.h
+++ b/src/soc/intel/skylake/chip.h
@@ -110,6 +110,9 @@ struct soc_intel_skylake_config {
/* PL4 Value in Watts */
u32 tdp_pl4;
+ /* Estimated maximum platform power in Watts */
+ u16 psys_pmax;
+
/*
* The following fields come from FspUpdVpd.h.
* These are configuration values that are passed to FSP during