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| author | Barnali Sarkar <barnali.sarkar@intel.com> | 2016-08-24 20:48:46 +0530 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-09-15 00:46:11 +0200 |
| commit | 5bf42c6c23b462d9292e6854d3f334cf17e42825 (patch) | |
| tree | 2a95d06c128f2fe97027e7fc46e9368399ab8504 /src/soc/intel/skylake/chip.h | |
| parent | 69966ccb5de0addda131f313b20515bfa0cb00c8 (diff) | |
| download | coreboot-5bf42c6c23b462d9292e6854d3f334cf17e42825.tar.xz | |
soc/intel/skylake: Add FSP 2.0 support in romstage
Populate SoC related Memory initialization params.
Post memory init, set DISB, setup stack and MTRRs using the postcar
funtions provided in postcar_loader.c.
TEST=Build and boot kunimitsu, dram initialization done.
ramstage is loaded.
Change-Id: I8d943e29b6e118986189166d92c7891ab6642193
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Reviewed-on: https://review.coreboot.org/16315
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/skylake/chip.h')
| -rw-r--r-- | src/soc/intel/skylake/chip.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index a4dee51b39..62e28e693c 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -359,6 +359,10 @@ struct soc_intel_skylake_config { * 011b - VR specific command sent for both MPS IMPV8 & PS4 exit issue */ u8 SendVrMbxCmd; + + /* Enable/Disable VMX feature */ + u8 VmxEnable; + /* Statically clock gate 8254 PIT. */ u8 clock_gate_8254; |