diff options
author | Felix Singer <felixsinger@posteo.net> | 2020-07-25 14:01:52 +0200 |
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committer | Michael Niewöhner <c0d3z3r0@review.coreboot.org> | 2020-07-29 20:58:58 +0000 |
commit | 91dfb920383a8761711e1312f2bcffd2f9529dfb (patch) | |
tree | c59d0834ada7b19e8dc6699c92697894447b4388 /src/soc/intel/skylake/chip.h | |
parent | aff69be254096a3a9d630551780c5610b7db15fa (diff) | |
download | coreboot-91dfb920383a8761711e1312f2bcffd2f9529dfb.tar.xz |
soc/intel/skylake: Enable HECI3 depending on devicetree configuration
Currently HECI3 gets enabled by the option Heci3Enabled, but
this duplicates the devicetree on/off options. Therefore use the
on/off options for the enablement of the HECI3 controller.
I checked all corresponding mainboards if the devicetree configuration
matches the Heci3Enabled setting.
Change-Id: I4f99d434dfee49a9783e38c3910b9391d479cb83
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43864
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/skylake/chip.h')
-rw-r--r-- | src/soc/intel/skylake/chip.h | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index 54d006915c..3f55c18b8b 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -315,7 +315,6 @@ struct soc_intel_skylake_config { u8 PttSwitch; u8 HeciTimeouts; u8 HsioMessaging; - u8 Heci3Enabled; /* Gfx related */ u8 IgdDvmt50PreAlloc; |