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| author | Wei Shun Chang <wei.shun.chang@intel.com> | 2018-04-09 11:46:43 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-08-20 15:58:52 +0000 |
| commit | b54d15487ace81af9e3a1f9f64a509624bb5081d (patch) | |
| tree | d843aa85422ea0fd0f02e23449a75ede49f60e2b /src/soc/intel/skylake/chip.h | |
| parent | 5d790e3f528808733676215e4c1040798223f1c7 (diff) | |
| download | coreboot-b54d15487ace81af9e3a1f9f64a509624bb5081d.tar.xz | |
soc/intel/skylake: Support PL1 override option
In legacy mode, DPTF on some systems may rely on MMIO to control PL1
settings. However, MSR PL1 also contributes to the decision of max
PL1 power; and in the current design, the lower value takes effect.
In order to align MMIO and MSR settings, a tdp_pl1_override option is
added to override the MSR PL1 limitation.
BRANCH=eve
BUG=b:73133864
TEST=1. Write PL1 override setting in devicetree.cb
2. Verify the MSR PL1 limitation is set correctly.
Change-Id: I35b8747ad3ee4c68c30d49a9436aa319360bab9b
Signed-off-by: Lucas Chen <lucas.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/28079
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc/intel/skylake/chip.h')
| -rw-r--r-- | src/soc/intel/skylake/chip.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index 8e3c472db6..ec8b461647 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -99,6 +99,8 @@ struct soc_intel_skylake_config { /* PL2 Override value in Watts */ u32 tdp_pl2_override; + /* PL1 Override value in Watts */ + u32 tdp_pl1_override; /* SysPL2 Value in Watts */ u32 tdp_psyspl2; |