diff options
| author | Subrata Banik <subrata.banik@intel.com> | 2018-05-09 14:55:09 +0530 |
|---|---|---|
| committer | Subrata Banik <subrata.banik@intel.com> | 2018-06-06 06:23:45 +0000 |
| commit | c4986eb7f4eee0f305c6a6f05b45effae152062c (patch) | |
| tree | 46185566d98e49bbfa60acfdedc60e1e423823d3 /src/soc/intel/skylake/chip.h | |
| parent | f513cebd8b966c15e3c8abcd2d0f540607ea5964 (diff) | |
| download | coreboot-c4986eb7f4eee0f305c6a6f05b45effae152062c.tar.xz | |
soc/intel/common/block: Add common chip config block
Adding common chip config structure which will be used to return data to
common code. When common code requires soc data, code used to fetch
entire soc config structure. With this change, common code will only get
the data/structure which is required by common code and not entire
config.
For now, adding i2c, gspi and lockdown configuration which will be used
by common code.
BUG=none
BRANCH=b:78109109
TEST=compile code for APL/SKL/CNL. Boot using SKL/APL/CNL and check
values are returned properly using common structure.
Change-Id: I7f1671e064782397d3ace066a08bf1333192b21a
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/26189
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Hannah Williams <hannah.williams@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/skylake/chip.h')
| -rw-r--r-- | src/soc/intel/skylake/chip.h | 25 |
1 files changed, 7 insertions, 18 deletions
diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index 8b98662b1e..3c85ad5a3d 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -3,7 +3,7 @@ * * Copyright (C) 2007-2008 coresystems GmbH * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015 Intel Corporation. + * Copyright (C) 2015-2018 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -22,6 +22,7 @@ #include <arch/acpi_device.h> #include <device/i2c_simple.h> #include <drivers/i2c/designware/dw_i2c.h> +#include <intelblocks/chip.h> #include <intelblocks/gspi.h> #include <stdint.h> #include <soc/gpe.h> @@ -33,14 +34,16 @@ #include <soc/usb.h> #include <soc/vr_config.h> -#define SKYLAKE_I2C_DEV_MAX 6 - enum skylake_i2c_voltage { I2C_VOLTAGE_3V3, I2C_VOLTAGE_1V8 }; struct soc_intel_skylake_config { + + /* Common struct containing soc config data required by common code */ + struct soc_intel_common_config common_soc_config; + /* * Interrupt Routing configuration * If bit7 is 1, the interrupt is disabled. @@ -273,11 +276,7 @@ struct soc_intel_skylake_config { /* I2C */ /* Bus voltage level, default is 3.3V */ - enum skylake_i2c_voltage i2c_voltage[SKYLAKE_I2C_DEV_MAX]; - struct dw_i2c_bus_config i2c[SKYLAKE_I2C_DEV_MAX]; - - /* GSPI */ - struct gspi_cfg gspi[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX]; + enum skylake_i2c_voltage i2c_voltage[CONFIG_SOC_INTEL_I2C_DEV_MAX]; /* Camera */ u8 Cio2Enable; @@ -544,16 +543,6 @@ struct soc_intel_skylake_config { * 0b - Disabled */ u8 eist_enable; - /* Chipset (LPC and SPI) Lock Down - * 1b - coreboot to handle lockdown - * 0b - FSP to handle lockdown - */ - enum { - /* lock according to binary UPD settings */ - CHIPSET_LOCKDOWN_FSP, - /* coreboot handles locking */ - CHIPSET_LOCKDOWN_COREBOOT, - } chipset_lockdown; /* * Activates VR mailbox command for Intersil VR C-state issues. |