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author | Nico Huber <nico.h@gmx.de> | 2017-09-19 09:36:03 +0200 |
---|---|---|
committer | Martin Roth <martinroth@google.com> | 2018-04-05 15:52:45 +0000 |
commit | 2afe4dc075fd2cab8d362aa026066a5f53663f2c (patch) | |
tree | b59930db3e2403c531697dbdccb87bdec1ee77e4 /src/soc/intel/skylake/chip.h | |
parent | db06cf0576192dca4ae4cdb185d311baffc4669c (diff) | |
download | coreboot-2afe4dc075fd2cab8d362aa026066a5f53663f2c.tar.xz |
soc/intel/skylake: Enable VT-d and X2APIC
We use the usual static addresses 0xfed90000/0xfed91000 for the GFX
IOMMU and the general IOMMU respectively. These addresses have to be
configured in MCHBAR registers (maybe, who knows, the blob is undocu-
mented), advertised to FSP and reserved from the OS.
The new devicetree option `ignore_vtd` allows to retain the old beha-
viour (do whatever pre-set UPD values suggest).
We also let FSP set up distinct BDFs for messages originating from the
I/O-APIC and the HPET.
Change-Id: I77f87c385736615c127143760bbd144f97986b37
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/21597
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Youness Alaoui <snifikino@gmail.com>
Diffstat (limited to 'src/soc/intel/skylake/chip.h')
-rw-r--r-- | src/soc/intel/skylake/chip.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index dc7986948f..2523554613 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -113,6 +113,9 @@ struct soc_intel_skylake_config { /* Estimated maximum platform power in Watts */ u16 psys_pmax; + /* Wether to ignore VT-d support of the SKU */ + int ignore_vtd; + /* * The following fields come from FspUpdVpd.h. * These are configuration values that are passed to FSP during |