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author | Subrata Banik <subrata.banik@intel.com> | 2019-07-08 14:49:22 +0530 |
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committer | Subrata Banik <subrata.banik@intel.com> | 2019-07-11 05:57:41 +0000 |
commit | 10a9432cc2ad77234442bd639194c5a80050854e (patch) | |
tree | ce6f68feab9582d2ab62765cd0d9a3262bb62b69 /src/soc/intel/skylake/chip_fsp20.c | |
parent | 5b9948140f97eceb47ba026d7bad6dfa2a3c483d (diff) | |
download | coreboot-10a9432cc2ad77234442bd639194c5a80050854e.tar.xz |
soc/intel/common/timer: Move USE_LEGACY_8254_TIMER into common/block/timer
This patch moves USE_LEGACY_8254_TIMER Kconfig into common/block/timer
for better code sharing. Also ported CB:33512 for SPT and ICP PCH.
Change-Id: Ic767ff97aaa3eb7fa35ffa38fa416d006eaa6e78
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34132
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc/intel/skylake/chip_fsp20.c')
-rw-r--r-- | src/soc/intel/skylake/chip_fsp20.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c index 08f5d79349..a1fced293d 100644 --- a/src/soc/intel/skylake/chip_fsp20.c +++ b/src/soc/intel/skylake/chip_fsp20.c @@ -315,6 +315,9 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) /* disable Legacy PME */ memset(params->PcieRpPmSci, 0, sizeof(params->PcieRpPmSci)); + /* Legacy 8254 timer support */ + params->Early8254ClockGatingEnable = !CONFIG_USE_LEGACY_8254_TIMER; + memcpy(params->SerialIoDevMode, config->SerialIoDevMode, sizeof(params->SerialIoDevMode)); |